DRP3510 Datasheet, PDF (17/30 Pages) List of Unclassifed Manufacturers – Digital Receiver Front-end

ADVANCE INFORMATION
DRX 3960A
Table 4–8: Write Register on I²C Subaddress 10_hex
I²C-Sub-
address
(hex)
Function
10 10
10 12
Reference divider setting
The DRX 3960A is able to operate with different reference frequencies. The
reference divider has to be set to the value which divides the reference fre-
quency to 100 kHz.
To prevent malfunction after POR, the default value is set for f_ref = 27 MHz, if
the pin REF_SW is connected to V_DVDD or set for f_ref = 20.25 MHz, if the pin
REF_SW is connected to GND.
bit[8:0]
External_Ref_Freq / 100 kHz
27 MHz
20.25 MHz
4 MHz
10D_hex
CA_hex
28_hex
Tuner Take Over Point (TOP) setting
Defines the gain of the internal preamplifier to set the TOP
bit[3:0]
Gain of Preamplifier
0
0 dB
1
1.33 dB
2
2.67 dB
...
8
10 dB (default)
...
14
18.67 dB
15
20 dB
10 70
Equalizer coefficient 0
bit[9:1]
bit[0]
Coefficient
Update bit
0
1
do not update coefficients
update coefficients
10 71
Equalizer coefficient 1
bit[8:0] Coefficient
10 72
Equalizer coefficient 2
bit[8:0] Coefficient
10 73
Equalizer coefficient 3
bit[8:0] Coefficient
Name
SYN_REF
TOP_SET
EQU_0
EQU_1
EQU_2
EQU_3
Micronas
17