DRP3510 Datasheet, PDF (22/30 Pages) List of Unclassifed Manufacturers – Digital Receiver Front-end

DRX 3960A
ADVANCE INFORMATION
Pin 37, ADR_SEL − I²C Bus address select
By means of this pin, one of three device addresses
can be selected.
Pin 39, DVDD_ADC − Digital supply pin for ADC
This pin has to be connected to 3.3 V.
Pin 40, DVSS_ADC − Digital ground pin for ADC.
This pin has to be connected to digital ground.
Pin 41, XTAL_IN − Crystal input pin
If an external clock is used this pin should be left open.
A crystal should be placed as close as possible to this
pin. External capacitors at each crystal pin to ground
are required. It should be verified by layout, that no
supply current is flowing through the ground connec-
tion point.
Pin 42, XTAL_OUT − Crystal output pin
If an external clock is used, it has to be connected to
this pin. A crystal should be placed as close as possi-
ble to this pin. External capacitors at each crystal pin
to ground are required. It should be verified by layout,
that no supply current is flowing through the ground
connection point.
Pin 43, VREF − Analog reference voltage
This pin must be connected to SGND via a circuitry
according to the application circuit.
Pin 43, SGND − Reference for analog ground
This pin must be connected separately to a single
ground point.
5.4. Pin Configuration
DVSS
DVSS_CAP
PORT0
PORT1
TUNER_AGC
DVDD
DVDD_CAP
I2C_SCL
I2C_SDA
RESETQ
TEST_EN
PORT2
PORT3
PORT4
ADR_SEL
PORT5
DVDD_ADC
DVSS_ADC
XTAL_IN
XTAL_OUT
VREF
SGND
33 32 31 30 29 28 27 26 25 24 23
34
22
35
21
36
20
37
19
38
18
39
DRX 3960A
17
40
16
41
15
42
14
43
13
44
12
1 2 3 4 5 6 7 8 9 10 11
AVSS_DAC
AVDD_DAC
SIF
REF_SW
CVBS
TEST2
TEST1
TEST0
SHIELD
AVSS_SYN
AVDD_SYN
AVSS_ADC
AVDD_ADC
ANATSTX
ANATSTY
AVDD_FE8
AVSS_FE40
IFINY
AVDD_FE40
IFINX
AVSS_FE40
AVSS_FE8
Fig. 5–2: 44-pin PMQFP package
22
Micronas