DRP3510 Datasheet, PDF (11/30 Pages) List of Unclassifed Manufacturers – Digital Receiver Front-end

ADVANCE INFORMATION
DRX 3960A
4. Control Interface
4.1. I²C Bus Interface
4.1.1. Device and Subaddresses
The DRX 3960A is controlled via the I²C bus slave
interface.
The IC is selected by transmitting one of the
DRX 3960A device addresses. In order to allow up to
three ICs to be connected to a single bus, an address
select pin (ADR_SEL) has been implemented. With
ADR_SEL pulled to high, low, or left open, the
DRX 3960A responds to different device addresses. A
device address pair is defined as a write address and a
read address.
Writing is done by sending the device write address,
followed by the subaddress byte, two address bytes,
and two data bytes. Reading is done by sending the
write device address, followed by the subaddress byte
and two address bytes. Without sending a stop condi-
tion, reading of the addressed data is completed by
sending the device read address and reading two
bytes of data.
Due to the internal architecture of the DRX 3960A, the
IC cannot react immediately to an I²C request. The
typical response time is about 0.3 ms. If the
DRX 3960A cannot accept another complete byte of
data until it has performed some other function (for
example, servicing an internal interrupt), it will hold the
clock line low to force the transmitter into a wait state.
The maximum wait period during normal operation
mode is less than 1 ms.
Table 4–1: I²C Bus Device Addresses
ADR_SEL
Mode
Device address
Write
82_hex
Low
Read
83_hex
Write
86_hex
High
Read
87_hex
Left Open
Write
Read
8A_hex
8B_hex
Table 4–2: I²C Bus Subaddresses
Name
CONTROL
Binary Value
0000 0000
Hex Value
00
PORT
0000 0011
03
WR_DRX
0001 0000
10
RD_DRX
0001 0001
11
Mode
Read/Write
Write
Write
Write
Function
Write
Read
: Software reset of DRX
: Hardware error status of DRX
output port address
write address
read address
Micronas
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