PE3293 Datasheet, PDF (7/18 Pages) List of Unclassifed Manufacturers – 1.8GHz/550MHz Dual Fractional-N Ultra-Low Spurious PLL for Frequency Synthesis

PE3293
Product Specification
Table 7. AC Characteristics
V_DD = 3.0 V, -40° C < T_A < 85° C, unless otherwise specified
Symbol
Parameter
Control Interface and Latches (see figure 6)
f_Clock
Serial data clock frequency
t_ClockH
Serial clock HIGH time
t_ClockL
Serial clock LOW time
t_DSU
Data set-up time to Clock rising edge
t_DHLD
Data hold time after Clock rising edge
t_LEW
LE pulse width
t_CLE
Clock falling edge to LE rising edge
t_LEC
LE falling edge to Clock rising edge
t_{Data Out}
Data Out delay after Clock falling edge (f_oLD pin)
Main Divider (Including Prescaler)
f_in1
Operating frequency
f_in2
Operating frequency
Pf_in1
Input level range
Pf_in2
Input level range
f_c
Comparison frequency
Reference Divider
f_r
Operating frequency
V_fr
Input sensitivity
Note 1: CMOS logic levels may be used if DC coupled.
Conditions
C_L = 50 pf
External AC coupling
External AC coupling
External AC coupling (note 1)
Min
Max Units
10
MHz
50
ns
50
ns
50
ns
10
ns
50
ns
50
ns
50
ns
90
ns
300
1800
MHz
45
550
MHz
-7
5
dBm
-10
5
dBm
10
MHz
50
MHz
0.5
V_P-P
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