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| PE3293 Datasheet, PDF (12/18 Pages) List of Unclassifed Manufacturers – 1.8GHz/550MHz Dual Fractional-N Ultra-Low Spurious PLL for Frequency Synthesis | |||
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PE3293
Product Specification
Phase Comparator Characteristics
PLL1 has the timing relationships shown below for fc1, fp1, LD1, UP1, and DOWN1. When C11 = HIGH, UP1
directs the internal PLL1 charge pump to source current and DOWN1 directs the PLL1 internal charge pump to
sink current. If C11 = LOW, UP1 and DOWN1 are interchanged.
PLL2 has the timing relationships shown below for fc2, fp2, LD2, UP2, and DOWN2. When C21 = HIGH, UP2
directs the internal PLL2 charge pump to source current and DOWN2 directs the PLL2 internal charge pump to
sink current. If C21 = LOW, UP2 and DOWN2 are interchanged.
Figure 7. Phase Comparator Timing Diagram
fc1 (2)
(Note 1)
fp1 (2)
(Note 1)
LD1 (2)
(Note 1)
UP1 (2)
DOWN1 (2)
fc leads fp
fc = fp
fc lags fp
fc lags fp
fc lags fp
Note 1: fc1(2), fp1(2), and LD1(2) are accessible via the foLD pin per programming in Table 11.
Copyright ï Peregrine Semiconductor Corp. 2003
Page 12 of 18
File No. 70/0015~02C | UTSi ï CMOS RFIC SOLUTIONS
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