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PE3293 Datasheet, PDF (6/18 Pages) List of Unclassifed Manufacturers – 1.8GHz/550MHz Dual Fractional-N Ultra-Low Spurious PLL for Frequency Synthesis
Table 6. DC Characteristics
VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified
Symbol
Parameter
IDD
3 V supply current
Istby
Total standby current
Digital inputs: Clock, Data, LE
VIH
High level input voltage
VIL
Low level input voltage
IIH
High level input current
IIL
Low level input current
Reference Divider input: fr
IIHR
Input current
IILR
Input current
Digital output: foLD
VOLD
Output voltage LOW
VOHD
Output voltage HIGH
Charge Pump outputs: CP1, CP2
ICP - Source
ICP - Sink
Drive current
ICPL
Leakage current
ICP – Source
vs.
ICP - Sink
Sink vs. source mismatch
ICP vs TA
Output current vs. temperature
ICP vs. VCP
Output current magnitude
variation vs. voltage
Conditions
C10, C20 = 00 (both PLLs on)
VDD = 2.7 to 3.3 volts
VDD = 2.7 to 3.3 volts
VIH = VDD = 3.3 volts
VIL = 0, VDD = 3.3 volts
VIH = VDD = 3.3 volts
VIL = 0, VDD = 3.3 volts
Iout = 1 mA
Iout = -1 mA
VCP = VDD / 2
0.5 V < VCP < VDD – 0.5 volt
VCP = VDD / 2, TA = 25° C
VCP = VDD / 2
0.5 V < VCP < VDD – 0.5 volt, TA = 25° C
PE3293
Product Specification
Min
0.7 x VDD
-1
-1
-25
VDD – 0.4
-5
Typ
Max
Units
4.0
mA
5.0
50
µA
V
0.3 x VDD
V
+1
µA
+1
µA
+25
µA
µA
0.4
V
V
-70
-70
5
10
10
10
µA
µA
nA
%
%
%
Copyright  Peregrine Semiconductor Corp. 2003
Page 6 of 18
File No. 70/0015~02C | UTSi  CMOS RFIC SOLUTIONS