PE3293 Datasheet, PDF (4/18 Pages) List of Unclassifed Manufacturers – 1.8GHz/550MHz Dual Fractional-N Ultra-Low Spurious PLL for Frequency Synthesis

PE3293
Product Specification
Pin No.
22
23
24
Pin Name Type
V_DD
N/C
(Note 1)
V_DD
(Note 1)
Same as pin 21.
No connect.
Same as pin 21.
Description
Note 1: V_DD pins 21, 22, and 24 are connected by diodes and must be supplied with the same voltage level.
PE3293 Description
The PE3293 is intended for such applications as
the local oscillator for the RF and first IF of dual-
conversion transceivers. The RF PLL (PLL1)
includes a 32/33 prescaler with a 1.8 GHz
maximum frequency of operation, where the IF
PLL (PLL2) incorporates a 16/17 prescaler with a
550 MHz maximum frequency of operation. Using
an advanced fractional-N phase-locked loop
technique, the PE3293 can generate a stable,
very low phase- noise signal. The dual fractional
architecture allows fine resolution in both PLLs,
with no degradation in phase noise performance.
Data is transferred into the PE3293 via a three-
wire interface (Data, Clock, LE). Supply voltage
can range from 2.7 to 3.3 volts for V_DD. PE3293
features very low power consumption and is
available in a JEDEC MO-153-AC (TSSOP), 20-
pin package and 24-lead BCC package.
Spurious Response
A critical parameter for synthesizer designs is
spurious output. Spurs occur at the integer
multiples of the step size away from center tone.
An important feature of fractional synthesizers is
their ability to reduce these spurious sidebands.
The PE3293 has a built-in method for reducing
these spurs, with no external components or
tuning required. In addition, this circuitry works
over the full commercial temperature and VCO
tuning range.
Copyright  Peregrine Semiconductor Corp. 2003
Page 4 of 18
File No. 70/0015~02C | UTSi  CMOS RFIC SOLUTIONS