PE3293 Datasheet, PDF (3/18 Pages) List of Unclassifed Manufacturers – 1.8GHz/550MHz Dual Fractional-N Ultra-Low Spurious PLL for Frequency Synthesis

PE3293
Product Specification
Figure 3. Pin Configuration: 24-Pin BCC (Top View)
GND ^fin2 Dec2V^DD2 LE
N/C 19 18 17 16 15 14 13 N/C
CP2 20
12 Data
V_DD 21
V_DD 22
N/C 23
11 Clock
10 f_oLD
9 GND
V_DD 24
8 f_r
N/C 1 2 3 4 5 6 7 N/C
CP1
GND
f_in1 _DEC1VDD1
Table 2. Pin Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Pin Name
N/C
Type
CP1
Output
GND
f_in1
Input
Dec1
V_DD1
N/C
f_r
GND
Input
f_oLD
Output
Clock
Data
N/C
LE
V_DD2
Dec2
f_in2
GND
N/C
CP2
Input
Input
Input
Input
Output
V_DD
(Note 1)
Description
No connect.
Internal charge-pump output from PLL1 for connection to a loop filter for driving the input of an external
VCO.
Ground
Prescaler input from the PLL1 (RF) VCO. Maximum frequency is 1.8 GHz.
Power supply decoupling pin for PLL1. A capacitor should be placed as close as possible to this pin and be
connected directly to the ground plane.
PLL1 prescaler power supply (FlexiPower 1).
No connect.
Reference frequency input.
Ground.
Multiplexed output of the PLL1 and PLL2 main counters or reference counters, Lock Detect signals, and
data out of the shift register. CMOS output (see Table 11, f_oLD Programming Truth Table).
CMOS clock input. Serial data for the various counters is clocked in on the rising edge into the 21-bit shift
register.
Binary serial data input. CMOS input data entered MSB first. The two LSBs are the control bits.
No connect.
Load Enable CMOS input. When LE is high, data word stored in the 21-bit serial shift register is loaded into
one of the four appropriate latches (as assigned by the control bits).
PLL2 prescaler power supply. 3.3 kohm resistor to V_DD.
Power supply decoupling pin for PLL2. A capacitor should be placed as close as possible to this pin and be
connected directly to the ground plane.
Prescaler input from the PLL2 (IF) VCO. Maximum frequency is 550MHz.
Ground.
No connect.
Internal charge-pump output for PLL2. For connection to a loop filter for driving the input of an external
VCO.
Power supply voltage input. Input may range from 2.7 V to 3.3 V. A bypass capacitor should be placed as
close as possible to this pin and be connected directly to the ground plane.
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