PE3293 Datasheet, PDF (2/18 Pages) List of Unclassifed Manufacturers – 1.8GHz/550MHz Dual Fractional-N Ultra-Low Spurious PLL for Frequency Synthesis

Figure 2. Pin Configuration: TSSOP (JEDEC MO-153-AC)
N/C 1
V_DD 2
CP1 3
GND 4
f_in1 5
Dec1 6
V_DD1 7
f_r 8
GND 9
f_oLD 10
20 V_DD
19 V_DD
18 CP2
17 GND
16 f_in2
15 DEC2
14 V_DD2
13 LE
12 Data
11 Clock
PE3293
Product Specification
Table 1. Pin Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin Name
N/C
Type
V_DD
(Note 1)
CP1
GND
f_in1
Output
Input
Dec1
V_DD1
f_r
GND
Input
f_oLD
Output
Clock
Data
LE
V_DD2
Dec2
f_in2
GND
CP2
V_DD
V_DD
Input
Input
Input
Output
Output
Input
Output
(Note 1)
(Note 1)
Description
No connect.
Power supply voltage input. Input may range from 2.7 V to 3.3 V. A bypass capacitor should be placed as
close as possible to this pin and be connected directly to the ground plane.
Internal charge-pump output from PLL1 for connection to a loop filter for driving the input of an external VCO.
Ground.
Prescaler input from the PLL1 (RF) VCO. Maximum frequency is 1.8 GHz.
Power supply decoupling pin for PLL1. A capacitor should be placed as close as possible to this pin and be
connected directly to the ground plane.
PLL1 prescaler power supply. 3.3 kohm resistor to V_DD.
Reference frequency input.
Ground.
Multiplexed output of the PLL1 and PLL2 main counters or reference counters, Lock Detect signals, and data
out of the shift register. CMOS output (see Table 11, f_oLD Programming Truth Table).
CMOS clock input. Serial data for the various counters is clocked in on the rising edge into the 21-bit shift
register.
Binary serial data input. CMOS input data entered MSB first. The two LSBs are the control bits.
Load Enable CMOS input. When LE is high, data word stored in the 21-bit serial shift register is loaded into
one of the four appropriate latches (as assigned by the control bits).
PLL2 prescaler power supply. 3.3 kohm resistor to V_DD.
Power supply decoupling pin for PLL2. A capacitor should be placed as close as possible to this pin and be
connected directly to the ground plane.
Prescaler input from the PLL2 (IF) VCO. Maximum frequency is 550 MHz.
Ground.
Internal charge-pump output for PLL2. For connection to a loop filter for driving the input of an external VCO.
Same as pin 2.
Same as pin 2.
Note 1: V_DD pins 2, 19, and 20 are connected by diodes and must be supplied with the same voltage level.
Copyright  Peregrine Semiconductor Corp. 2003
Page 2 of 18
File No. 70/0015~02C | UTSi  CMOS RFIC SOLUTIONS