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SI5311 Datasheet, PDF (6/24 Pages) List of Unclassifed Manufacturers – PRECISION HIGH SPEED CLOCK MULTIPLIER/REGENERATOR IC
Si5311
Table 2. DC Characteristics, VDD = 2.5 V
(VDD = 2.5 V ± 5%, TA = –40°C to 85°C)
Parameter
Symbol Test Condition Min
Typ
Max Unit
Supply Current
MULTSEL[1:0] = 00
MULTSEL[1:0] = 01
MULTSEL[1:0] = 10
MULTSEL[1:0] = 11
IDD
—
108
118
mA
—
113
123
—
117
127
—
124
134
Power Dissipation
MULTSEL[1:0] = 00
MULTSEL[1:0] = 01
MULTSEL[1:0] = 10
MULTSEL[1:0] = 11
PD
—
270
310
mW
—
283
323
—
293
333
—
310
352
Common Mode Input Voltage
(CLKIN, REFCLK)
VICM
See Figure 2
—
.80 " VDD
—
V
Input Voltage Range*
VIS
See Figure 2
—
(CLKIN+, CLKIN–, REFCLK+, REFCLK–)
—
750
mV
Differential Input Voltage Swing*
(CLKIN, REFCLK)
VID
See Figure 2
200
—
1500 mV
(pk-pk)
Input Impedance (CLKIN, REFCLK)
Differential Output Voltage Swing
(CLKOUT)
RIN
Line-to-Line
84
100
116
Ω
VOD
100 Ω Load
TBD
940
TBD
mV
Line-to-Line
(pk-pk)
Differential Output Voltage Swing
(MULTOUT)
VOD
100 Ω Load
TBD
900
TBD
mV
Line-to-Line
(pk-pk)
Output Common Mode Voltage
(CLKOUT, MULTOUT)
VOCM
100 Ω Load
— VDD – 0.7 —
V
Line-to-Line
Output Impedance (CLKOUT, MULTOUT)
ROUT
Single-ended
84
100
116
Ω
Output Short to GND (CLKOUT, MULTOUT) ISC(–)
—
25
TBD
mA
Output Short to VDD (CLKOUT, MULTOUT) ISC(+)
TBD
–15
—
mA
Input Voltage Low (LVTTL Inputs)
VIL
—
—
.8
V
Input Voltage High (LVTTL Inputs)
VIH
2.0
—
—
V
Input Low Current (LVTTL Inputs)
IIL
—
25
TBD
µA
Input High Current (LVTTL Inputs)
IIH
—
25
TBD
µA
Output Voltage Low (LVTTL Outputs)
VOL
IO = 2 mA
—
—
0.4
V
Output Voltage High (LVTTL Outputs)
VOH
IO = 2 mA
2.0
—
—
V
Input Impedance (LVTTL Inputs)
RIN
100
—
—
kΩ
PWRDN/CAL Internal Pulldown Current
IPWRDN VPWRDN ≥ 0.8 V TBD
25
TBD
µA
*Note: The CLKIN and REFCLK inputs may be driven differentially or single-endedly. When driving single-endedly, the voltage
swing of the signal applied to the active input must exceed the specified minimum Differential Input Voltage Swing (VID
min) and the unused input must be ac-coupled to ground. When driving differentially, the difference between the
positive and negative input signals must exceed VID min. (Each individual input signal needs to swing only half of this
range.) In either case, the voltage applied to any individual pin (CLKIN+, CLKIN–, REFCLK+, or REFCLK–) must not
exceed the specified maximum Input Voltage Range (VIS max).
6
Preliminary Rev. 0.6