SI5311 Datasheet, PDF (1/24 Pages) List of Unclassifed Manufacturers – PRECISION HIGH SPEED CLOCK MULTIPLIER/REGENERATOR IC

Si5311
PRELIMINARY DATA SHEET
PRECISION HIGH SPEED CLOCK MULTIPLIER/REGENERATOR IC
Features
Complete precision high speed clock multiplier and regenerator device:
! Performs Clock Multiplication to
One of Four Frequency Ranges:
150–167 MHz, 600–668 MHz,
1.2–1.33 GHz, or 2.4–2.67 GHz
! Jitter Generation as low as
0.5 ps_RMS for 622 MHz Output
! Accepts Input Clock from
9.4–668 MHz
! Regenerates a “Clean”, Jitter-
Attenuated Version of Input
Clock
! DSPLL™ Technology Provides
Superior Jitter Performance
! Small Footprint: 4 mm x 4 mm
! Low Power: 310 mW typical
Applications
! SONET/SDH Systems
! Terabit Routers
! Digital Cross Connects
! Optical Transceiver Modules
! Gigabit Ethernet Systems
! Hybrid VCO Modules
Description
The Si5311 is a fully integrated high-speed clock multiplier and clock
regenerator IC. The clock multiplier generates an output clock that is an
integer multiple of the input clock. When the clock multiplier is operating in
either the 150–167 MHz range or the 600–668 MHz range, the clock
regenerator operates simultaneously. The clock regenerator creates a
“clean” version of the input clock by using the clock synthesis phase-
locked loop (PLL) to remove unwanted jitter and square up the input
clock’s rising and falling edges. The Si5311 uses Silicon Laboratories
patented DSPLL^™ architecture to achieve superior jitter performance while
eliminating the analog loop filter found in traditional PLL designs.
The Si5311 represents a new standard in low jitter, small size, low power,
and ease-of-use for high speed clock devices. It operates from a single
2.5 V supply over the industrial temperature range (–40°C to 85°C).
Functional Block Diagram
Ordering Information:
See page 22.
Pin Assignments
Si5311
20 19 18 17 16
REXT 1
15 PWRDN/CAL
VDD 2
GND 3
REFCLK+ 4
GND
Pad
14 VDD
13 CLKOUT+
12 CLKOUT–
REFCLK– 5
11 VDD
6 7 8 9 10
Top View
C LK IN +
C LK IN –
2
BUF
D S P L L ^TM
P h a se -L o c ke d
Loop
2
2
R egeneration
2
BUF
C alibration
2
BUF
B ias G en
C L K O U T+
C L K O U T–
P W R D N /C AL
M ULTOUT+
M ULTOUT–
LOL
REFCLK+ M ULTSEL1–0
REFCLK–
REXT
Preliminary Rev. 0.6 6/01
Copyright © 2001 by Silicon Laboratories
Si5311-DS06
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.