SI5311 Datasheet, PDF (17/24 Pages) List of Unclassifed Manufacturers – PRECISION HIGH SPEED CLOCK MULTIPLIER/REGENERATOR IC

Si5311
with the input clock. During reacquisition, the multiplier
output (MULTOUT) will drift over a range of
approximately 1% relative to the supplied reference
clock. The LOL output will remain asserted until the
divided multiplier output frequency differs from the
REFCLK frequency by less than the amount specified in
Table 4.
Note: LOL is not asserted during PWRDN/CAL.
PLL Performance
The Si5311 DSPLL circuitry is designed to provide low
jitter generation, high jitter tolerance, and a well-
controlled jitter transfer function with low peaking. Each
of these key performance parameters is described more
fully in the following sections.
Jitter Tolerance
Jitter tolerance for the Si5311 is defined as the
maximum peak-to-peak sinusoidal jitter that can be
added to the incoming clock before the PLL exceeds its
allowable operating range and loses lock. The tolerance
is a function of the jitter frequency, the incoming clock
rate, and the MULTSEL0/1 settings.
The jitter tolerance for specified jitter frequencies and
input clock rates is given in Tables 5, 6, 7, and 8.
Jitter Transfer
Jitter transfer is defined as the ratio of output signal jitter
to input signal jitter for a specified jitter frequency. The
jitter transfer characteristic determines the amount of
input clock jitter that will be passed on to the Si5311
CLKOUT and MULTOUT outputs. The DSPLL
technology used in the Si5311 provides a tightly
controlled jitter transfer curve because many of the PLL
gain parameters are determined by digital signal
processing algorithms which do not vary over supply
voltage, process, and temperature. In a system
application, a well-controlled transfer curve minimizes
the output clock jitter variation from board to board,
providing more consistent system level jitter
performance.
The jitter transfer characteristic is a function of the
MULTSEL0/1 settings and the input clock rate. Higher
input clock rates produce higher bandwidth transfer
functions with lower jitter peaking. Table 4 gives the
3 dB bandwidth and peaking values for specified input
clock rates and MULTSEL0/1 settings. Figures 6, 7, 8,
and 9 show a family of jitter transfer curves for different
input clock rates.
Jitter Generation
Jitter generation is defined as the amount of jitter
produced at the output of the device with a jitter free
input clock. Generated jitter arises from sources within
the VCO and other PLL components. Jitter generation is
a function of MULTSEL0/1 settings and input clock
frequency. For clock multiplier applications, the higher
the multiplier ratio desired, the larger the jitter
generation. Table 4 gives the jitter generation values for
specified MULTSEL0/1 settings and input clock rates.
PLL Jitter Transfer Functions (MULTSEL[1:0]=00) (dB)
0
CLKIN=622MHz
−1
−2
−3
−4
−5
−6
−7
−8
−9
10³
10⁴
10⁵
10⁶
Figure 6. PLL Jitter Transfer Functions,
MULTSEL[1:0] = 00
(MULTOUT = 2400–2672 MHz)
PLL Jitter Transfer Functions (MULTSEL[1:0]=01) (dB)
0
CLKIN=622MHz
−1
−2
−3
−4
CLKIN=311MHz
−5
−6
−7
−8
−9
10³
10⁴
10⁵
10⁶
Figure 7. PLL Jitter Transfer Functions,
MULTSEL[1:0] = 01
(MULTOUT = 1200–1336 MHz)
Preliminary Rev. 0.6
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