SI5311 Datasheet, PDF (18/24 Pages) List of Unclassifed Manufacturers – PRECISION HIGH SPEED CLOCK MULTIPLIER/REGENERATOR IC

Si5311
PLL Jitter Transfer Functions (MULTSEL[1:0]=10) (dB)
0
CLKIN=622MHz
−1
−2
−3
−4
CLKIN=39MHz
−5
−6
−7
−8
−9
10³
10⁴
10⁵
10⁶
Figure 8. PLL Jitter Transfer Functions,
MULTSEL[1:0] = 10
(MULTOUT = 600–668 MHz)
PLL Jitter Transfer Functions (MULTSEL[1:0]=11) (dB)
0
CLKIN=155MHz
−1
−2
−3
−4
CLKIN=9.7MHz
−5
−6
−7
−8
−9
10³
10⁴
10⁵
10⁶
Figure 9. PLL Jitter Transfer Functions,
MULTSEL[1:0] = 11
(MULTOUT = 150–167 MHz)
Device Power-Down
The Si5311 PWRDN/CAL input can be used to hold the
device in a power-down state when not in use. When
the PWRDN/CAL input is asserted (set high), the
CLKOUT and MULTOUT output drivers are disabled
and the positive and negative terminals of the CLKOUT
and MULTOUT outputs are each tied to VDD through
100 Ω on-chip resistors. This feature is useful in
reducing power consumption in applications that
employ redundant clock sources. When PWRDN/CAL is
released (set to low) the digital logic is reset to a known
initial condition and the DSPLL circuitry is recalibrated
and will begin to lock to the incoming clock.
PLL Self-Calibration
Si5311 device provides an internal self-calibration
function that optimizes the loop gain parameters within
the internal DSPLL. Self-calibration is initiated by a
high-to-low transition of the PWRDN/CAL signal while a
valid reference clock is supplied to the REFCLK input.
For optimal jitter performance, the supply voltage
should be stable at 2.5 V ±10% when calibration is
initiated. The PWRDN/CAL signal should be held high
for at least 1 µS after the supply has stabilized before
transitioning low to initiate self-calibration. See Silicon
Laboratories application note AN42 for suggested
methods of generating the PWRDN/CAL signal for
initiation of self-calibration.
Device Grounding
The Si5311 uses the GND pad on the bottom of the 20-
pin micro leaded package (MLP) for device ground. This
pad should be connected directly to the analog supply
ground. See Figures 12 and 13 for the ground (GND)
pad location.
Bias Generation Circuitry
The Si5311 makes use of an external resistor to set
internal bias currents. The external resistor allows
precise generation of bias currents which significantly
reduces power consumption compared with traditional
implementations that use an internal resistor. The bias
generation circuitry requires a 10 kΩ (1%) resistor
connected between REXT and GND.
Differential Input Circuitry
The Si5311 provides differential inputs for both the input
clock (CLKIN) and the reference clock (REFCLK)
inputs. An example termination for these inputs is
shown in Figure 10. In applications where direct dc
coupling is possible, the 0.1 µF capacitors may be
omitted. The CLKIN and REFCLK input amplifiers
require input signals with minimum differential peak-to-
peak voltages as specified in Table 2 on page 6.
Differential Output Circuitry
The Si5311 utilizes a current mode logic (CML)
architecture to output both the regenerated clock
(CLKOUT) and the multiplied clock (MULTOUT). An
example of output termination with ac coupling is shown
in Figure 11. For applications in which direct dc coupling
is possible, the 0.1 µF capacitors may be omitted. The
differential peak-to-peak voltage swing of the CML is
listed in Table 2 on page 6.
18
Preliminary Rev. 0.6