SI5311 Datasheet, PDF (16/24 Pages) List of Unclassifed Manufacturers – PRECISION HIGH SPEED CLOCK MULTIPLIER/REGENERATOR IC

Si5311
DSPLL^™
The PLL structure (shown in Figure 1 on page 4) utilizes
Silicon Laboratories' DSPLL technology to produce
superior jitter performance while eliminating the need
for external loop filter components found in traditional
PLL implementations. This is achieved by using a digital
signal processing (DSP) algorithm to replace the loop
filter commonly found in analog PLL designs. This
algorithm processes the phase detector error term and
generates a digital control value to adjust the frequency
of the voltage controlled oscillator (VCO). The
technology produces clocks with less jitter than is
generated using traditional methods. In addition,
because external loop filter components are not
required, sensitive noise entry points are eliminated,
thus making the DSPLL less susceptible to board-level
noise sources.
Clock Multiplier
The DSPLL phase locks to the clock input signal
(CLKIN) and generates an output clock (MULTOUT) at
a multiple of the input clock frequency. The MULTOUT
output is configured to operate in the 150–167 MHz, the
600–668 MHz, the 1.2–1.33 GHz, or the 2.4–2.67 GHz
frequency range using the MULTSEL0 and MULTSEL1
control inputs as indicated in Table 11. Values for typical
applications are given in Table 12.
The amount of jitter present in the MULTOUT output is a
function of the DSPLL jitter transfer function and jitter
generation characteristic. Details are provided in the
PLL Performance section of this document. (See
Figures 6, 7, 8, and 9.) The amount of jitter that the
DSPLL can tolerate on the CLKIN input is specified in
Tables 5, 6, 7, and 8.
The DSPLL implementation in the Si5311 is insensitive
to the duty cycle of the CLKIN input. The MULTOUT
output will continue to exhibit a very good duty cycle
characteristic even when the CLKIN input duty cycle is
degraded.
1x Multiplication
The Si5311 Clock Multiplier function may also be
utilized as a 1x multiplier in order to provide jitter
attenuation and duty cycle correction without
multiplication of the input clock frequency.
Note: When the Si5311 is configured as a 1:1 multiplier, the
CLKOUT output is not valid.
Clock Regeneration
When the MULTOUT output is configured to operate in
either the 150–167 MHz or the 600–667 MHz range, the
Si5311 clock regeneration (CLKOUT output) is also
provided. In this case, the DSPLL is used to regenerate
a jitter-attenuated version of the CLKIN input, resulting
in a “clean” CLKOUT output with sharp rising and falling
edges. The CLKOUT output is a resampled version of
the CLKIN input with all CLKOUT transitions occurring
synchronously with the rising edges of the MULTOUT
output. The rising edges of CLKOUT are insensitive to
the location of the falling edges of the CLKIN input.
Thus the period of CLKOUT, measured rising edge to
rising edge, is not affected by the CLKIN duty cycle or
by jitter on the falling edge of CLKIN.
The falling edges of CLKOUT may be affected by the
location of the CLKIN falling edges as follows: If the
duty cycle error of CLKIN is significant relative to the
period of MULTOUT, then
1. The CLKOUT duty cycle may deviate from 50% (the falling
edge of CLKOUT will be time quantized to the nearest
rising edge of MULTOUT.)
2. Jitter on the falling edges of CLKIN may result in a
CLKOUT duty cycle that alternates between two discrete
values.
Note: When the Si5310 is configured as a 1:1 multiplier, the
CLKOUT output is not valid.
Reference Clock
The reference clock input (REFCLK) is used to center
the DSPLL and also to act as a reference for
determination of the PLL lock status. REFCLK is a
multiple of the CLKIN frequency, and can be provided in
any one of five frequency ranges (9.375–10.438 MHz,
18.78–20.875 MHz, 37.500–41.750 MHz, 75.00–
83.50 MHz, or 150–167.00 MHz). The REFCLK rate is
automatically detected by the Si5311, so no control
inputs are needed for REFCLK frequency selection. The
REFCLK input may be synchronous or asynchronous
with respect to the CLKIN input. The frequency
relationship between REFCLK and CLKIN is indicated
in Table 11. In many applications, it may be desirable to
tie REFCLK and CLKIN together and drive them from
the same clock source. The Si5311 is insensitive to the
phase relationship between CLKIN and REFCLK, so
these differential inputs may be driven in phase or 180°
out of phase if this simplifies board layout. Values for
typical applications are given in Table 12.
DSPLL Lock Detection (Loss-of-Lock)
The Si5311 provides lock-detect circuitry that indicates
whether the DSPLL has frequency locked with the
incoming CLKIN signal. The circuit compares the
frequency of a divided down version of the multiplier
output with the frequency of the supplied reference
clock. If the divided multiplier output frequency deviates
from that of the reference clock by the amount specified
in Table 4 on page 8, the PLL is declared out of lock,
and the loss-of-lock (LOL) pin is asserted.
While out of lock, the DSPLL will try to reacquire lock
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Preliminary Rev. 0.6