SI5311 Datasheet, PDF (14/24 Pages) List of Unclassifed Manufacturers – PRECISION HIGH SPEED CLOCK MULTIPLIER/REGENERATOR IC

Si5311
Functional Description
The Si5311 is an integrated high speed clock multiplier
and clock regenerator device based on Silicon
Laboratories DSPLL™ technology. The DSPLL phase
locks to the clock input signal (CLKIN) and generates a
phase-locked output clock (MULTOUT) at a multiple of
the input clock frequency. The MULTOUT output is
configured to operate in the 150–167 MHz, the 600–
668 MHz, the 1.2–1.33 GHz, or the 2.4–2.67 GHz
frequency range using the MULTSEL0 and MULTSEL1
control inputs.
When the device is configured for a MULTOUT output
frequency range of 150–167 MHz or 600–668 MHz, the
DSPLL is also employed to regenerate an output clock
(CLKOUT) that is a jitter-attenuated version of the input
clock with clean rising and falling edges. The CLKOUT
output is not characterized for the MULTOUT ranges of
1.2–1.33 GHz or 2.4–2.67 GHz.
A reference clock input signal (REFCLK) is used by the
DSPLL as a reference for determination of the PLL lock
status. For convenience, REFCLK can be provided at
any one of five frequencies, each a multiple of the
CLKIN frequency. The REFCLK rate is automatically
detected, so no control inputs are needed for
configuration. The REFCLK input can be synchronous
or asynchronous with respect to the CLKIN input. The
operating ranges for the CLKIN, CLKOUT, MULTOUT,
and REFCLK signals are indicated in Table 11. Values
for typical applications are given in Table 12.
Table 11. CLKIN, CLKOUT, MULTOUT, REFCLK Operating Ranges
MULTSEL [1:0]
CLKIN
Range (MHz)
REFCLK = 2ⁿ x CLKIN
±100 ppm
(see Note 2)
CLKOUT
MULTOUT
00
(MULTOUT = 2.4–2.7 GHz)
600.00–668.00 n = –6, –5, –4, –3, or –2 See Note 1(a) 4xCLKIN
01
(MULTOUT = 1.2–1.33 GHz)
300.00–334.00
600.00–668.00
n = –5, –4, –3, –2, or –1 See Note 1(a)
n = –6, –5, –4, –3, or –2 See Note 1(a)
4xCLKIN
2xCLKIN
37.500–41.750
n = –2, –1, 0, 1, or 2
1xCLKIN
16xCLKIN
10
(MULTOUT = 600–668 MHz)
75.000–83.500
150.000–167.000
300.000–334.000
n = –3, –2, –1, 0, or 1
n = –4, –3, –2, –1, or 0
n = –5, –4, –3, –2, or –1
1xCLKIN
1xCLKIN
1xCLKIN
8xCLKIN
4xCLKIN
2xCLKIN
600.000–668.000 n = –6, –5, –4, –3, or –2 See Note 1(b) 1xCLKIN
9.375–10.438
n = 0, 1, 2, 3, or 4
1xCLKIN
16xCLKIN
11
(MULTOUT = 150–167 MHz)
18.750–20.875
37.500–41.750
75.000–83.500
n = –1, 0, 1, 2, or 3
n = –2, –1, 0, 1, or 2
n = –3, –2, –1, 0, or 1
1xCLKIN
1xCLKIN
1xCLKIN
8xCLKIN
4xCLKIN
2xCLKIN
150.000–167.000 n = –4, –3, –2, –1, or 0 See Note 1(b) 1xCLKIN
Note:
1. The CLKOUT output is not valid for (a) MULTSEL[1:0] = 00 or MULTOUT[1:0] = 01
(b) MULTOUT:CLKIN ratios of 1:1 (MULTOUT = 1 x CLKIN.)
2. The REFCLK input can be set to any one of the five CLKIN multiples indicated. The REFCLK input can be
asynchronous to the CLKIN input, but must be within ±100 ppm of the stated CLKIN multiple.
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