SD1010A Datasheet, PDF (38/45 Pages) List of Unclassifed Manufacturers – Analog-Interface XGA TFT LCD Display Controller

SmartASIC, Inc.
SD1010A
Bit[6:2]: sharpness-enhanced level
Level 1 – 19. Level “5” is the same as the original
source. From “4” to “1” intend to soften the picture,
and “1” is the softest level. From level “6” to “19” will
sharpen the picture gradually. Level “19” is the
sharpest output.
Bit[7]: Reserved
Control_E
Default is 14H
8 RW 54H[7:0] Control Register E
Bit[3:0]: text enhancement threshold.
Bit[4]: reserved
Bit[6:5]: Frame Modulation Mode
0: compatible with SD1010
1-3: new schemes
Bit[7]: reserved
Pixel_h
Pixel_v
Pixle_out
Fc3_start
Channel_select
Dual_pixel
Soft_start
ICS_phase_state
Hsize_by842_en
Video_mode
Input_yuv
Yuv_signed
decimation
Detect_en
November, 1999
Revision B
Default is 05H
11 RW 55H[10:8] The x location for reading “Pixel_out” register
56H[7:0]
11 RW 57H[10:8] The y location for reading “Pixel_out” register
58H[7:0]
24
R 59H, 5AH, Read out pixel located by “Pixel_h” and “Pixel_v”
5BH
1 RW 5CH[4] Forces auto calibration to recalculate h back porch
1 RW 5CH[3] Only for single pixel input
0: takes input data from channel 1
1: takes input data from channel 0
For 128 pin package, set this bit at 0
1 RW 5CH[2] 0: takes input from one single channel
1: takes input from both channels.
For 128 pin package, set this bit at 0
1 RW 5CH[1] Restarts auto calibration without going into reset
1 RW 5CH[0] Forces auto calibration to calculate the image quality
for a particular clock phase when supplied by ics chips
1 RW 5DH[7] Turn on internal hsize matching by8, 4, 2 when clock
frequency calibration is done by8, 4, 2. Used mainly
for special non-full screen inputs.
1 RW 5DH[6] 0: disable input video mode
1: input is video
1 RW 5DH[5] 0: input video format is RGB
1: input video format is YUV 4:2:2
1 RW 5DH[4] 0: input video YUV format is unsigned
1: input video YUV format is signed
1 RW 5DH[3] Used when input resolution is higher than output
1: enable special decimation control
0: disable special decimation
2 RW 5DH[2:1] Input data range detection. The results are put in
register 64H and 65H
SmartASIC Confidential
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