SD1010A Datasheet, PDF (10/45 Pages) List of Unclassifed Manufacturers – Analog-Interface XGA TFT LCD Display Controller

SmartASIC, Inc.
SD1010A
G_OUT1_E
48
O Output Color Green Even Pixel (left pixel)
G_OUT2_E
49
O Output Color Green Even Pixel (left pixel)
G_OUT3_E
50
O Output Color Green Even Pixel (left pixel)
G_OUT4_E
51
O Output Color Green Even Pixel (left pixel)
G_OUT5_E
53
O Output Color Green Even Pixel (left pixel)
G_OUT6_E
54
O Output Color Green Even Pixel (left pixel)
G_OUT7_E
55
O Output Color Green Even Pixel (left pixel)
G_OUT0_O
58
O Output Color Green Odd Pixel (right pixel)
G_OUT1_O
59
O Output Color Green Odd Pixel (right pixel)
G_OUT2_O
60
O Output Color Green Odd Pixel (right pixel)
G_OUT3_O
61
O Output Color Green Odd Pixel (right pixel)
G_OUT4_O
63
O Output Color Green Odd Pixel (right pixel)
G_OUT5_O
64
O Output Color Green Odd Pixel (right pixel)
G_OUT6_O
65
O Output Color Green Odd Pixel (right pixel)
G_OUT7_O
66
O Output Color Green Odd Pixel (right pixel)
B_OUT0_E
69
O Output Color Blue Even Pixel (left pixel)
B_OUT1_E
70
O Output Color Blue Even Pixel (left pixel)
B_OUT2_E
71
O Output Color Blue Even Pixel (left pixel)
B_OUT3_E
72
O Output Color Blue Even Pixel (left pixel)
B_OUT4_E
73
O Output Color Blue Even Pixel (left pixel)
B_OUT5_E
74
O Output Color Blue Even Pixel (left pixel)
B_OUT6_E
75
O Output Color Blue Even Pixel (left pixel)
B_OUT7_E
78
O Output Color Blue Even Pixel (left pixel)
B_OUT0_O
80
O Output Color Blue Odd Pixel (right pixel)
B_OUT1_O
81
O Output Color Blue Odd Pixel (right pixel)
B_OUT2_O
82
O Output Color Blue Odd Pixel (right pixel)
B_OUT3_O
83
O Output Color Blue Odd Pixel (right pixel)
B_OUT4_O
85
O Output Color Blue Odd Pixel (right pixel)
B_OUT5_O
86
O Output Color Blue Odd Pixel (right pixel)
B_OUT6_O
87
O Output Color Blue Odd Pixel (right pixel)
B_OUT7_O
88
O Output Color Blue Odd Pixel (right pixel)
HSYNC_O
21
O Output HSYNC (the polarity is programmable
through CPU, default is active low)
VSYNC_O
22
O Output VSYNC (the polarity is programmable
through CPU, default is active low)
DCLK_OUT
23
O Output Clock to Control Panel (the polarity is
programmable through CPU)
DE_OUT
24
O Output Display Enable for Panel (the polarity is
programmable through CPU, default is active HIGH)
FCLK0
VCLK0
17
O Input PLL Feedback Clock
18
I Input Clock 0
FCLK1
VCLK1
19
O Output PLL Feedback Clock
20
I Output PLL Output Clock
ROM_SCL
ROM_SDA
1
O SCL in I²C for EEPROM interface
2
I/O SDA in I²C for EEPROM interface
CPU_SCL
4
I SCL in I²C for CPU interface
November, 1999
SmartASIC Confidential
10
Revision B