SD1010A Datasheet, PDF (15/45 Pages) List of Unclassifed Manufacturers – Analog-Interface XGA TFT LCD Display Controller

SmartASIC, Inc.
SD1010A
The PWM signal from the SD1010A is a periodical signal with a period that is 1023
times the period of the free-running clock connected to the pin “CLK_1M”. System
manufacturers may select any frequency for the free running clock. The default clock
frequency is 1MHz. System manufacturers also decide the unit delay for the external
delay circuit. The delay information is stored in the EEPROM. When the SD1010A
wants to delay the synchronization pulse for N units of delay, it will output the PWM
with the high time equal to (N * the period of the free-running clock), and with low
time equal to (1023-N)* the period of the free-running clock. When N=1023, the
PWM signal stays high all the time, and when N=0, the PWM signal is always low.
Figure 3: SD1010 PWM circuitry block diagram
SD1010A
Synchronization pulse
PWM
Delay
Circuitry
Ref_Clk
PLL
3.1.5.
Free Running Clock
As described in previous section, a free-running clock is needed for the SD1010A.
This clock is used for many of the SD1010A’s internal operations. PWM operation is
one of them. System manufacturers can select the frequency of the free-running clock,
and the default clock frequency is 1MHz. System manufacturers can use an oscillator
to generate the free-running clock, and feed that clock directly to the pin “CLK_1M”,
or use a crystal connecting to “CLK_1M” and “CLK_1M_O”.
3.2.
Buffer memory and read/write control block
The SD1010A uses internal buffer memory to store a portion of the input image for
image scaling and output synchronization. No external memory buffer is needed for
the SD1010A. The write control logic ensures the input data are stored into the right
area of the buffer memory, and the read control logic is responsible to fetch the data
from the buffer memory from the correct area and at the correct timing sequence.
With the precise timing control of the write and read logic, the output image is
appropriately scaled to the full screen, and the output signal is perfectly synchronized
with the input signals.
November, 1999
SmartASIC Confidential
15
Revision B