SD1010A Datasheet, PDF (37/45 Pages) List of Unclassifed Manufacturers – Analog-Interface XGA TFT LCD Display Controller

SmartASIC, Inc.
SD1010A
Recovery Control
8
Phase Range
4
Phase Track
24
Waiting Time
Quick Phase
1
Enable
PWM Enable
1
Standalone Enable 1
Reserved Entry
1
Phase Offset
10
Phase Total
10
Image Quality Index 30
Text Control
8
Sharpness Control 8
Bit [7:3]: Reserved
RW 44H Clock Recovery Control Register:
Default value is 71H
Bit 0: clock frequency is divisible by 2
Bit 1: clock frequency is divisible by 4
Bit 2: clock frequency is divisible by 8
Bit 3: enable phase tracking feature
Bit 4: enable auto phase calibration
Bit 5: enable auto frequency calibration
Bit 6: enable auto mode detection
Bit 7: fixed at 0 (reserved)
RW 45H Offset value added to the calibrated phase when phase
tracking occurs
RW 46H Number of frames waited before phase tracking occurs
48H
RW 49H[0] 0: Normal phase calibration (default)
1: Final phase = phase total – phase offset
RW 49H[1] 0: Disable auto phase total calculation
1: Enable auto phase total calculation (default)
RW 49H[2] 0: Uses the external incoming SYNC signals
(default)
1: Allow the use of the default SYNC signals
instead of the incoming SYNC signals
RW 49H[3] Fixed at 0 (reserved)
RW 4AH Offset value subtracted from phase total when doing
4BH quick phase calculation
RW 4CH User defined value for a particular frequency
4DH
R 4EH[5:0],4 Read only register for CPU to monitor Image Quality
FH, 50H, Index. The Image Quality Index is used by auto phase
51H calibration.
RW 52H[7:0] Text-Enhancement Control
Bit[0]: text enhancement enable
0: disable
1: enable
Bit[1]: Reserved
Bit[6:2]: text-enhanced level
Level 0 – 14. Level “0” is the same as original source,
and “14” is the highest enhancement level.
Bit[7]: Reserved
Default is 00H
RW 53H[7:0] Sharpness-Enhancement Control
Bit[0]: sharpness enhancement enable
0: disable
1: enable
Bit[1]: Reserved
November, 1999
SmartASIC Confidential
37
Revision B