SD1010A Datasheet, PDF (27/45 Pages) List of Unclassifed Manufacturers – Analog-Interface XGA TFT LCD Display Controller

SmartASIC, Inc.
SD1010A
0: disable SYNC polarity based mode detection
bit 0: 640x350 bit 1: 640x400 bit 2: 720x400
bit 3: 640x480 bit 4: 800x600 bit 5: 832x624
bit 6: 1024x768 bit 7: res mode1 bit 8: res mode2
bit 9: res mode3 bit 10: res mode4 bit 11: res mode5
bit 12: res mode6 bit 13: res mode7
Maximum VBP
8
221H The maximum vertical back porch for input video
Reserved Entries
8
222H-255H Set to all 0 or all 1 (reserved)
Data low threshold
8
256H Low water mark for valid data.
If the data is smaller than this threshold, it is considered
LOW internally
Data high threshold
8
257H High water mark for valid data.
If the data is larger than this threshold, it is considered
HIGH internally
Edge threshold
8
258H Minimum difference between the data value of two
adjacent pixels to be considered as an edge
Calibration mode
2
259H [1:0] Selects different operation modes of internal phase
calibration. The selection criterion is as follows:
0: when input video signal has large overshot,
it results in longest calibration time
1: when input video signal has median overshot,
it results in long calibration time
2: when input video signal has normal overshot,
it results in normal calibration time
(recommended)
3: when input video signal has no overshot,
it results in shortest calibration time
PWM unit delay
16 25AH-25BH The unit delay used in the external PWM delay circuitry.
If the free-running clock is 1MHz, and the intended unit
delay is 0.2 ns (= 5,000MHz), then a value of
5,000MHz/1MHz = 5,000 is used here.
Maximum link off time 22 25CH-25EH Maximum time when input VSYNC is off before the
LINK_DWN pin turns ON (unit: clock period of the free
running clock). If the free-running clock is 1MHz, and the
intended maximum time is 1 second, then a value of
1,000,000 µs/ 1 µs = 1,000,000 is used here.
Maximum refresh rate
16 25FH-260H Maximum refresh rate supported by the LCD panel.
If the intended maximum refresh rate is 75Hz, and the
free-running clock is 1MHz, then a value of
1000000/75=133,333 is used here
Maximum input
8
261H Maximum source clock rate supported by the SD1010
frequency
(unit: frequency of free-running clock).
If the intended maximum clock rate is 60MHz, and the
free-running clock is 1MHz, then a value of 60 is used
here.
If the input signal has a higher frequency than this value,
the VCLK0_X status bit will turn ON.
Minimum pixels per line 11 262H-263H Minimum number of pixels per line for LCD panel
for LCD
LCD polarity
4 264H[3:0] _{Controls the polarity of output VSYNC,}
HSYNC, clock and display enable:Bit0: 0: clock
active high, 1: clock active low
Bit1: 0: HSYNC active low, 1: HSYNC active high
Bit2: 0: VSYNC active low, 1: VSYNC active high
November, 1999
SmartASIC Confidential
27
Revision B