SD1010A Datasheet, PDF (25/45 Pages) List of Unclassifed Manufacturers – Analog-Interface XGA TFT LCD Display Controller

SmartASIC, Inc.
SD1010A
Control byte 2
Mode 640x350
Sync Polarity
Res0 threshold
[10:8]
Res0 threshold
[7:0]
Mode 640x400
Sync Polarity
Res1 threshold
[10:8]
Res1 threshold
[7:0]
Mode 720x400
Sync Polarity
Res2 threshold
[10:8]
Res2 threshold
[7:0]
Mode 640x480
Sync Polarity
Res3 threshold
[10:8]
Res3 threshold
[7:0]
Mode 800x600
Sync Polarity
Res4 threshold
[10:8]
Res4 threshold
[7:0]
Mode 832x624
Sync Polarity
Res5 threshold
November, 1999
Revision B
Bit3: fixed at 0 (reserved)
Bit4: 0: YUV input format is unsigned (128 offset)
1: YUV input format is signed
Bit5: 0: RGB input for video mode
1: YUV input for video mode
Bit6: 0: disable video input
1: enable video input
Bit7: 0: disable decimation support
1: enable decimation
8
202H Bit 0: 0: don’t invert input odd/even field indicator
1: invert input odd/even field indicator
Bit 1: fixed at 0 (reserved)
Bit 2: 0: disable BY2 for auto calibration
1: enable BY 2 for auto calibration
Bit 3: 0: disable BY4 for auto calibration
1: enable BY 4 for auto calibration
Bit 4: 0: disable BY8 for auto calibration
1: enable BY 8 for auto calibration
Bit7-5: output clock phase adjustment, larger number
gives larger phase delay.
2
203H[5:4] The polarity of input synchronization signals.
Bit 0 is for VSYNC and bit 1 is for HSYNC
3
203H[2:0] Upper bound of the line number for 640x350 mode
8
204H Upper bound of the line number for 640x350 mode, and
lower bound for 640x400
2
205H[5:4] The polarity of input synchronization signals.
Bit 0 is for VSYNC and bit 1 is for HSYNC
3
205H[2:0] Upper bound of the line number for 640x400 mode
8
206H Upper bound of the line number for 640x400 mode, and
lower bound for 720x400
2
207H[5:4] The polarity of input synchronization signals.
Bit 0 is for VSYNC and bit 1 is for HSYNC
3
207H[2:0] Upper bound of the line number for 720x400 mode
8
208H Upper bound of the line number for 720x400 mode, and
lower bound for 640x480
2
209H[5:4] The polarity of input synchronization signals.
Bit 0 is for VSYNC and bit 1 is for HSYNC
3
209H[2:0] Upper bound of the line number for 640x480 mode
8
20AH Upper bound of the line number for 640x480 mode, and
lower bound for 800x600
2
20BH[5:4] The polarity of input synchronization signals.
Bit 0 is for VSYNC and bit 1 is for HSYNC
3
20BH[2:0] Upper bound of the line number for 800x600 mode
8
20CH Upper bound of the line number for 800x600 mode, and
lower bound for 832x624
2
20DH[5:4] The polarity of input synchronization signals.
Bit 0 is for VSYNC and bit 1 is for HSYNC
3
20DH[2:0] Upper bound of the line number for 832x624 mode
SmartASIC Confidential
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