SD1010A Datasheet, PDF (30/45 Pages) List of Unclassifed Manufacturers – Analog-Interface XGA TFT LCD Display Controller

SmartASIC, Inc.
SD1010A
Gamma_scale6_g
8
293H Gamma_scalefactor6 for green
Gamma_scale7_g
8
294H Gamma_scalefactor7 for green
Gamma_scale0_b
8
295H Gamma_scalefactor0 for blue
Gamma_scale1_b
8
296H Gamma_scalefactor1 for blue
Gamma_scale2_b
8
297H Gamma_scalefactor2 for blue
Gamma_scale3_b
8
298H Gamma_scalefactor3 for blue
Gamma_scale4_b
8
299H Gamma_scalefactor4 for blue
Gamma_scale5_b
8
29AH Gamma_scalefactor5 for blue
Gamma_scale6_b
8
29BH Gamma_scalefactor6 for blue
Gamma_scale7_b
8
29CH Gamma_scalefactor7 for blue
Gamma_offset0_r
8
29DH Gamma_offset0 for red
Gamma_offset1_r
8
29EH Gamma_offset1 for red
Gamma_offset2_r
8
29FH Gamma_offset2 for red
Gamma_offset3_r
8
2A0H Gamma_offset3 for red
Gamma_offset4_r
8
2A1H Gamma_offset4 for red
Gamma_offset5_r
8
2A2H Gamma_offset5 for red
Gamma_offset6_r
8
2A3H Gamma_offset6 for red
Gamma_offset7_r
8
2A4H Gamma_offset7 for red
Gamma_offset0_g
8
2A5H Gamma_offset0 for green
Gamma_offset1_g
8
2A6H Gamma_offset1 for green
Gamma_offset2_g
8
2A7H Gamma_offset2 for green
Gamma_offset3_g
8
2A8H Gamma_offset3 for green
Gamma_offset4_g
8
2A9H Gamma_offset4 for green
Gamma_offset5_g
8
2AAH Gamma_offset5 for green
Gamma_offset6_g
8
2ABH Gamma_offset6 for green
Gamma_offset7_g
8
2ACH Gamma_offset7 for green
Gamma_offset0_b
8
2ADH Gamma_offset0 for blue
Gamma_offset1_b
8
2AEH Gamma_offset1 for blue
Gamma_offset2_b
8
2AFH Gamma_offset2 for blue
Gamma_offset3_b
8
2B0H Gamma_offset3 for blue
Gamma_offset4_b
8
2B1H Gamma_offset4 for blue
Gamma_offset5_b
8
2B2H Gamma_offset5 for blue
Gamma_offset6_b
8
2B3H Gamma_offset6 for blue
Gamma_offset7_b
8
2B4H Gamma_offset7 for blue
Check sum
8
2B5H Sum of all part 9 bytes (keep only lower 8 bit)
3.6. CPU interface
The SD1010A supports a 2-wire serial interface to an external CPU. The interface
allows the external CPU to access and modify control registers inside the SD1010A.
The 2-wire serial interface is similar to the EEPROM interface, and the CPU is the
host that drives the SCL all the time as the clock and for “start” and “stop” bits. The
SCL frequency can be as high as 5MHz. The SDA is a bi-directional data wire. This
interface supports random and sequential write operations for the CPU to modify one
or multiple control registers, and random and sequential read operations for the CPU
to read all or part of the control registers.
November, 1999
SmartASIC Confidential
30
Revision B