MC34921 Datasheet, PDF (30/36 Pages) List of Unclassifed Manufacturers – Configurable Motor Driver IC with Power Supplies

FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Table 15. NORMAL Mode Output Frame Programming Model
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
A/Dd7 A/Dd6 A/Dd5 A/Dd4 A/Dd3 A/Dd2 A/Dd1 A/Dd0 Info A/Dr2 A/Dr1 A/Dr0 DENCB DENCA A/Ddone2 A/Ddone1
Table 16. NORMAL Mode Output Frame Bit Allocation Model
Bit
Bit Name
Bit Description
15 – 8
A/Dd[7:0] ADC data from last conversion.
7
Info
Identifies the output frame as a normal or information frame. The type of output frame is determined by the IREQ
bit (Bit 1) in the Configuration mode input frame.
6 –4
A/Dr[2:0] Report the input to the ADC that is represented in the A/Dd[7:0] (Bits 15–8).
3–2
DENCB, Analog encoder interface digital signals. These signals are used to drive a quadrature encoder on the MCU.
DENCA
1–0
A/Ddone2, Flag completion of the ADC for corresponding conversion. If ADC in single conversion mode, only A/Ddone1 is
A/Ddone1 asserted. If in double conversion mode, A/Ddone1 is asserted for first conversion and A/Ddone2 is asserted for
second conversion
NFO (IREQ) MODE:
NFO (IREQ) Mode is the mode in which the MC34921 IC reports status and error information via the serial interface.
Table 17. NFO (IREQ) Mode Output Frame Programming Model I
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
0
0
0
1
1
0
EXT B+UV Info V5VUV 3.3UV CoreU DENC DENC TSD
V
B
A
Bit 0
TW
Table 18. INFO (IREQ) Mode Output Frame Bit Allocation
Bit
Bit Name
Bit Description
15 – 10
9
8
Reserved
EXT
B+UV
These bits will report [011000].
This flag will report if the last generated reset was due to an external signal driving RST.
Undervoltage flag for the B+ input voltage. If the input voltage drops below that necessary for the 34921 to
operate, this flag will be asserted.
7
Info
Identifies the output frame as a normal or information frame. The type of output frame is determined by the IREQ
bit (Bit 1) in the Configuration mode input frame.
6
V5VUV
Undervoltage warning for the 5.0 V regulator. This will be asserted when a fault on the 5.0 V causes the voltage
to droop.
5
3.3UV
Undervoltage warning for the 3.3 V regulator. This will be asserted when a fault on the 3.3 V causes the voltage
to droop.
4
CoreUV
Undervoltage warning for the VCORE linear regulator. This will be asserted when a fault on the VCORE voltage
causes the voltage to droop.
3–2
DENCB,
Analog encoder interface digital signals. These signals are used to drive a quadrature encoder on the MCU.
DENCA
1
TSD
Thermal shutdown flag. This flag will report if the last generated reset was due to a TSD. Thermal shutdown
occurs when the junction temperature reaches approximately 140ºC.
0
TW
Thermal warning flag. This bit is asserted when the junction temperature on the die reaches approximately
110ºC.
34921
30
Analog Integrated Circuit Device Data
Freescale Semiconductor