MC34921 Datasheet, PDF (20/36 Pages) List of Unclassifed Manufacturers – Configurable Motor Driver IC with Power Supplies

FUNCTIONAL DESCRIPTION
FUNCTIONAL TERMINAL DESCRIPTION
state. This means the MISO pin shows the status of the most
significant bit (bit 15) of the output frame until the first rising
edge of SCLK after the CE pin is taken to a logic low state.
The shift register will then shift data out on the MISO pin on
each subsequent rising edge of SCLK while CE is held in the
logic low state. During transfers, the most significant bit
(MSB) is transferred first. After all 16 bits have been
transferred, if any additional clocks are given while CE is in a
logic low state, the data is undefined and should be ignored.
MASTER OUT SLAVE IN (MOSI)
This is the master-out-slave-in terminal; the serial input
port of the Serial I/O, which typically connects to the MOSI of
a microprocessor. It has two frames of operation - NORMAL
and CONFIG, which are set by a bit in the NORMAL
frame.The MOSI pin is used for serial instruction data input.
MOSI information is clocked into the input shift register on the
rising edge of SCLK. A logic high state present on MOSI will
program a register bit on. The specific bit will turn on with the
16th rising edge of SCLK after placing the CE pin in a logic
low state. Conversely, a logic low state present on the MOSI
pin will program the register bit off. The specific bit will turn off
with the 16th rising edge of SCLK after placing the CE pin in
a logic low state. For each rising edge of the SCLK while CE
is logic low, a data bit instruction (on or off) is loaded into the
shift register per the data bit MOSI state. The last bit clocked
in (bit 0) is the CONFIG bit. If this bit is in a logic high state at
the 16th rising edge of SCLK after lowering the CE pin, the
bits in the shift register will be loaded into the CONFIG
register. If the bit is in a low logic state, the bits will be loaded
into the NORMAL register. Care should be taken to keep the
MOSI pin in a logic low state when it is not being used for
transfers to avoid erroneous data. During transfers, the most
significant bit (MSB) is clocked in first.
SERIAL CLOCK (SCLK)
As the serial clock terminal, the SCLK pin clocks the
internal shift registers of the MC34921. The serial data input
(MOSI) pin data is latched into the input shift register on the
rising edge of the 16th clock after the falling edge of the chip
select (CE) pin. The serial data output (MISO) pin shifts data
out of the shift register on the rising edge of the SCLK signal.
False clocking of the shift register must be avoided to ensure
validity of data. It is essential that one rising edge of SCLK
occur while CE is in a logic high state to ensure the correct
output data is latched into the output shift register. Clocking
the SCLK pin for more than one clock period while CE is in a
logic high state is not recommended and may have undesired
effects. For this reason, it is recommended that the SCLK pin
be clocked only once while CE is in a logic high state. The
MC34921 is designed such that SCLK should be a
continuous clock. This ensures that A/D sample rates are
held as constant as possible.
CHIP ENABLE (CE)
The chip enable port of the Serial I/O, typically connects to
the CE of a microprocessor. The logic state of the CE pin
activates clocking in and shifting out of data in and out of the
MC34921. While the CE pin is in the logic high state, the
output data in the NORMAL registers and the INFO registers
are latched (depending on the state of the IREQ bit in the
previous communication frame) in on each rising edge of the
clock such that the state of the MSB (bit 15) is readable on
the serial data output (MISO) pin. When CE is in a low logic
state both the input shift register and output shift register shift
data at the rising edge of SCLK.
MOTOR DRIVER C PWM INPUT A (CPWMA /CDCPWM)
This is the PWM logic input for the SA/SA/CDCM motor
drivers. The motor driver outputs follow this signal.
MOTOR DRIVER C PWM INPUT B (CPWMB)
This is the PWM logic input for the SB/SB motor drivers.
The motor driver outputs follow this signal.
DIGITAL GROUND (DGND)
This terminal is used for the Serial I/O and A/D converter
logic grounds, and should be kept isolated from the Analog
ground on the application PCB.
MOTOR DRIVER A PWM INPUT (APWM)
The PWM logic input terminal for the ADCM motor drivers.
The motor driver outputs follow this signal.
MOTOR DRIVER B PWM INPUT (BPWM)
The PWM logic input terminal for the BDCM motor drivers.
The motor driver outputs follow this signal.
MOTOR DRIVER C STEP MOTOR OUTPUT OR HIGH-
SIDE OUTPUT 2 (CDCMB / HSOUT2)
The high-side driver output is configurable for either C DC
motor control (as CDCMB, it requires external hardwire to pin
4), or as a general purpose high-side driver (HSOUT2) via the
serial I/O. The CDCMB is PWM controlled via the CPWMA/
CDCPWM pin. The direction and HSOUT2 are controlled via
the serial I/O. It includes current limit and thermal shutdown
protection.
MOTOR DRIVER C STEP MOTOR OUTPUT OR HIGH-
SIDE OUTPUT 1 (CDCMA / HSOUT1)
The high-side driver output is configurable for either C DC
motor control (as CDCMA, it requires external hardwire to pin
4), or as a general purpose high-side driver (HSOUT1) via the
serial I/O. The CDCMA is PWM controlled via the CPWMA/
CDCPWM pin. The direction and HSOUT1 are controlled via
the serial I/O. It includes current limit and thermal shutdown
protection.
34921
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Analog Integrated Circuit Device Data
Freescale Semiconductor