MC34921 Datasheet, PDF (26/36 Pages) List of Unclassifed Manufacturers – Configurable Motor Driver IC with Power Supplies

FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
Table 7. A/D Input Conversion Channel Addressing
NORMAL
Input
Frame
Bit 2
NORMAL
Input
Frame
Bit 3
NORMAL
Input
Frame
Bit 4
NORMAL
Output
Frame
Bit 2⁽²⁷⁾
NORMAL
Output
Frame
Bit 3⁽²⁷⁾
Input(s) Selected
A/Da0
0
1
1
1
1
1
1
0
0
1
A/Da1
0
0
1
1
1
1
0
0
1
1
A/Da2
0
0
0
0
0
0
1
1
1
1
DENCA
X
X
1
0
1
0
X
X
X
X
DENCB
X
X
0
1
1
0
X
X
X
X
AN0/ANALOGOUT_A terminal
AN1/ANALOGOUT_B terminal
Analog encoder interface output A
Analog encoder interface output A
Analog encoder interface output B
Analog encoder interface output B
Analog encoder interface outputs A and A with S/H ⁽²⁸⁾
Analog encoder interface outputs A and B with S/H ⁽²⁸⁾
Analog encoder interface outputs B and B with S/H ⁽²⁸⁾
AN2/ANALOGIN_A and AN3/ANALOGIN_B terminals (direct input) with
S/H ⁽²⁸⁾
Notes
Notes
27. DENCA and DENCB values are captured at the output of the 3 or 6 Edge filter on SCLK rising edge, then immediately
shifted out in the MISO data when CE is high.
28. Inputs are listed in order of conversion.
A/D Conversion Flow
There is a START conversion bit in the serial channel. The
presence of this bit begins a conversion cycle on the input(s)
selected in that frame. If the ADC is converting when a
subsequent START bit arrives, this start request will be
ignored. Figure 13, A/D Converter Input Structure, page 27,
shows how this process works. The current conversion
completes during the frame prior to the data being returned.
If there is a START bit in that input frame, another conversion
is begun as the previous conversion’s data is being shifted
out. If there is no START bit in the input frame, then another
conversion is begun the frame following receipt of the start
bit. The single conversion rate is paced at four frames for
configuration bit 3 =0 or eight frames (or less) for
configuration bit 3 =1, including sampling time (refer to
Table 13, CONFIG Input Frame Bit Allocation, page 29). In
order to simplify implementation of the 34921, the user must
ensure that no A/D conversions are in progress when an
INFO word is requested. For input pairs, the inputs are listed
in the order of conversion in Table 7.
Start
Idle
A2Ddone1 = 0
Start
A2Ddone2 = 0
A/Da=Last Address
Convert
A/Dd = Last
Conversion
A2Ddone1 = 0
A2Ddone2 = 0
A/Da = Current
Address
A/Dd = Last
Conversion
Conversion
Start
Done
Send Data
Start
Start
Start
Send Data2
A2Ddone1 = 0
A2Ddone2 = 1
A/Da = Current
Address
A/Dd = Current
Conversion
A2Ddone1 = 0
A2Ddone2 = 0
A2Da = Current
Address
A2Dd = Current
Conversion
A/Da = 1
Conversion
Done
Convert2
A2Ddone1 = 0
A2Ddone2 = 0
A/Da = Current
Address
A/Dd = Last
Conversion
Note “Start” is bit 1 of the serial input normal frame.
34921
26
Analog Integrated Circuit Device Data
Freescale Semiconductor