MC34921 Datasheet, PDF (25/36 Pages) List of Unclassifed Manufacturers – Configurable Motor Driver IC with Power Supplies

FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
I/V Conversion Stage
The I/V conversion stage is carried out by a
transimpedance amplifier using an external resistor. There is
a resistor to ground at the ANALOGIN_x input to allow offset
current trim and force the proper bias point on the encoder.
The feedback resistor should be sized to accommodate
±2.5 V output voltage swing for the full encoder current
waveform. For example, if the encoder produces a ±50 µA
signal, the feedback resistor needs to be 50 kΩ.
The resistor to ground must have a specific relationship to
the feedback resistor. It needs to be 1.17 times the feedback
resistor, or 58.5 kΩ for the example above. This ensures that
the encoder is biased at 1.35 V, and that the output of the
transimpedance amplifier is 2.5 V.
The I/V conversion stage can trim an encoder offset
current of up to ±8.0 µA in the encoder output.
Variable Gain Amplifier
The I/V conversion stage is followed by a variable gain
amplifier that can compensate for variations in the encoder
output. This is designed to accommodate manufacturing
variations in the encoder, as well as aging and other effects.
The gain can be changed over the serial interface at any time.
The output of the variable gain amplifiers can be routed to
the ANALOGOUT_x terminals for engineering evaluation.
Otherwise, these terminals are general purpose A/D inputs.
Channel Inversion and Digital Phase Generation
The A and B channels are inverted by applying the
function CHANNELx = 2.5 V - CHANNELx. This results in four
signals: A, B, A, and B. These signals are used produce the
digital encoder signals DENCA and DENCB, which are
converted by the ADC to provide the analog position
information. The value of the DENCA and DENCB signals
determine which signal—A, B, A, or B—is converted. Refer to
Table 7, page 26, for more information.
Position Information
The entire position information is produced by
concatenating the value of the a quadrature counter, driven
by DENCA and DENCB bits, and the 8 bits of “fractional”
information from the ADC.
Calibration of the Encoder
It is necessary to adjust the gain and offset of the I/V circuit
initially and periodically to compensate for encoder-to-
encoder variation, aging, and other effects. The ADC “double
conversion” function allows this by continuously sampling the
A and B signals, allowing a map of the encoder output to be
built up. The user will need to provide the necessary
algorithm to use the waveform map to produce gain and
offset calibration values for both channels.
ANALOG-TO-DIGITAL CONVERTER
Introduction
There is an 8-bit analog-to-digital converter (ADC) on the
34921 IC that uses the on-board voltage reference and
derives all the necessary timing signals from the SCLK input.
The ADC is referenced to the same ground as the system
ground (GND).
ADC Input Selection
The ADC has an 8-channel analog multiplexer so that all
inputs share one ADC. The input(s) to be converted are
determined by the A/Da[2:0] bits in the serial normal input
frame (refer to Table 11, page 28).
Three different types of conversion can occur (refer to
Table 7):
•Single Conversion 00X does a single conversion of
inputs AN0/ANALOGOUT_A or AN1/ANALOGOUT_B.
•Double Conversion 1XX does a double conversion of
channels A and B, A and A, B and B, or
AN2/ANALOGIN_A and AN3/ANALOGIN_B,
respectively.
•Auto-Select Conversion 011 does a single conversion
of one of the outputs from the analog encoder interface,
as selected by the digital outputs of the analog encoder
interface, DENCA and DENCB.
Analog Integrated Circuit Device Data
Freescale Semiconductor
34921
25