MC34921 Datasheet, PDF (29/36 Pages) List of Unclassifed Manufacturers – Configurable Motor Driver IC with Power Supplies

FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
CONFIG MODE:
Configuration mode is the mode in which the IC is programmed or configured by the external digital subsystem via the serial
interface (i.e., MOSI, MISO, SCLK, CE).
Table 12. CONFIG Mode Input Frame Programming Model
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Mtest1 Mtest0 cal4 cal3 cal2 cal1 cal0 ^ANALOG caladdr caladdr Filter DC SS A/D sleep IREQ config
(MSB)
(LSB)
_TEST
MODE
1
0
Speed
Table 13. CONFIG Input Frame Bit Allocation ⁽³²⁾
Bit
Bit Name
Bit Description
15 – 14
13 – 9
8
7–6
Mtest[1:0]
cal[4:0]
ANALOG_TEST
MODE
caladdr[1:0]
Reserved for Freescale test. Set to [10].
Data for various calibration registers.
Routes A and B output of analog encoder interface to AN0 and AN1, respectively. Used only for user
development and verification. Do not use in normal operation.
Determines the calibration register, as identified in Table 14 below, the calibration data in the cal[4:0] (Bits
13–9) bits is latched in.
5
Filter
Determines the number of SCLK edges used to filter the DENCA and DENCB signals coming from the Digital
Signal Generation stage of the analog encoder interface. This digital filter filters the DENCA and DENCB
signals made available to the serial output frame.
4
DC SS
Determines if Motor Driver C operates in DC motor or step motor mode. Implicitly determines whether
HSOUTx or LSOUTx are available. In DC motor mode, LSOUTx are available; in step motor mode, HSOUTx
are available.
3
A/D Speed Determines how many SCLK edges are required for conversion. This allows the use of a faster SCLK but still
maintains A/D conversion accuracy.
2
sleep
When asserted, causes the 34921 to enter a power-down state, and minimize power consumption.
1
IREQ
Causes the next output frame sent to the host to contain internal information from the 34921.
0
config
The input frame can be either a configuration frame or a normal frame. Bit 0 determines the type of frame being
received. Bit 0 = 1 is a configuration mode input frame.
Notes
32. All defaults = 0 at power up.
Table 14. Calibration Register Addressing
caladdr0
caladdr1
0
0
Channel A gain
1
0
Channel A offset
0
1
Channel B gain
1
1
Channel B offset
Register
Analog Integrated Circuit Device Data
Freescale Semiconductor
34921
29