MC34921 Datasheet, PDF (23/36 Pages) List of Unclassifed Manufacturers – Configurable Motor Driver IC with Power Supplies

FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
External N-FET Gate Drive Output
The GATEOUT terminal is an output for a high-side
N-channel MOSFET gate drive. The output will be used to
drive an external high-side MOSFET switch (see figure
below). When enabled, GATEOUT will be connected to the
V_b supply. The edge rates when switching the transistors
must be controlled so that shoot-through current does not
affect B+.
GATEOUT
V_b
Bit
GATEOUT
R_{S B+}
C_S
Figure 10. External N-FET Gate Drive Circuit
Clocking Schemes
There are two basic clocking schemes that can be used
while clocking data into the MC34921 IC. One has 16 rising
edges of SCLK while CE is in a logic low state and the other
has 15 rising edges of SCLK. In the 15 SCLK clocking
scheme, the input data and output data are latched on the
same clock edge. In the timing diagram on page 16, the
numbers on the MOSI line are the bits that will be clocked into
the input shift register at the rising edge of SCLK. They are
drawn occurring before SCLK to account for the required
setup time (minimum 15ns). The numbers on the MISO line
are the bits that will be clocked out at the rising edge of SCLK.
They are drawn occurring after SCLK to account for the
output delay from the rising edge of SCLK (maximum 40ns).
The numbers on the SCLK line are for reference only.
Note: when using the 15 bit clocking method with exactly
one rising edge of SCLK when CE is in a logic high state, the
output data to be sent out is latched at the same time the
IREQ bit is latched in. The next frame following the assertion
of the IREQ bit is the IREQ data. I.e., the frame after the
sending of the IREQ bit will have the data from the IREQ
register rather than skipping one frame. Note: regarding the
reporting of the DONE bit after the completion of an A/D
conversion: the DONE bit is sent out every time a conversion
completes. This requires the user to hold the MOSI pin in a
low state when it is not being used to transmit data. Refer to
Figure 4, Serial Interface Timing and Figure 5, Step Motor
Crossover Delay Timing
Analog Integrated Circuit Device Data
Freescale Semiconductor
SUPERVISORY (RST) FUNCTION
Supervisory Circuitry
The supervisor circuitry provides control of the RST line, an
open drain signal, based on system operating conditions
monitored by the 34921 IC. V _5.0, V_3.3, V_CORE, B+, and
thermal shutdown detectors in various parts of the chip are
monitored for error conditions. Because other devices in the
system may trigger a reset, the RST line itself is also
monitored, but the supervisor circuitry controls all reset
timing, including externally generated resets. Driving the RST
line low causes the system to be held in the reset state. V_5.0,
V_3.3, V_CORE, B+, and TSD have both positive- and negative-
going thresholds.
Static Operating Specifications
The state of RST is guaranteed as long as the minimum
supervisor operating conditions of B+ ≥ 9.0 V and V_5.0 ≥
2.0 V and V_3.3 ≥ 1.5 V and V_CORE are met. Once all these
conditions are met, RST is dependent on system operating
conditions. During initial power-up, RST is held low if any one
of the following error conditions is present: +5.0 V(low),
V_CORE(low), +3.3 V(low), B+(low), or TSD. Once all voltages
reach their positive-going threshold, RST is set high after the
appropriate timing.
Dynamic Operating Specifications
The RST is a bidirectional signal with an open drain output
driver and a CMOS digital input gate (see Figure 11). This I/
O structure allows wired OR connection to the CPU’s RST I/
O terminal, as well as allowing the CPU to initiate a reset
cycle by driving its RST terminal low. When responding to a
CPU request for a reset cycle, the 34921 IC must respond
rapidly enough to prevent a glitch. Figure 6, RST Timing,
page 17, shows the timing parameters for responding to an
externally applied RST signal.
To Internal
Registers
From
Internal
Reset
Circuits
RST
C_LOAD
Optional
Figure 11. RST Terminal Interface
The rise time with the open drain circuit may be relatively
slow, and the internal RST input gate must operate reliably
(no oscillations during the transition) under these conditions;
i.e., the RST input can be inhibited for up to t_phsl (max). Error
conditions must be present for a minimum time, t_filter, before
the 34921 responds to them. Once all error conditions are
cleared, RST is held low for an additional time of t_delay,
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