MC34921 Datasheet, PDF (24/36 Pages) List of Unclassifed Manufacturers – Configurable Motor Driver IC with Power Supplies

FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
128 SCLK periods. If any monitored item falls below its
negative-going threshold for t _filter, 1.5 µs to 5.0 µs, the t_delay
count is restarted when system operating conditions are met,
regardless of whether the t_delay count has been completed.
The trigger for the t_delay retriggerable one shot is
([+5.0 V(low) + 3.3 V(low) + V_CORE (low) + B+(low) + TSD]
and t_filter), where t_filter is the 1.5 µs to 5.0 µs delay.
RST and Thermal Shutdown State (TSD) Definition
There are seven registers in the INFO output word where
the trigger for the reset is recorded. This includes externally
generated resets as well as all the fault conditions listed in the
Supervisory Functions section of this datasheet. These
registers will remain valid as long as B+ ≥ 9.0 V. The fault
registers will only be cleared upon an externally generated
RST and will not be guaranteed for B+ < 9.0 V; i.e., initial
power-up or a serious B+ fault. The EXT bit will only be set
upon an externally generated reset.
Whenever RST is asserted and TSD is not set, the MISO
terminal will enter a high-impedance state, all the step motor
outputs will be off, and all the DC motor low-side drives will
be on. In addition, all internal data registers excepting the
RST fault registers in the INFO output word will be set to their
default values.
The thermal shutdown circuitry will monitor the chip’s
internal temperature at various points. The overtemperature
circuitry will disable all circuitry on the 34921 IC with the
exception of the RST output. RST will be asserted when the
temperature exceeds 140°C. This condition will be
maintained (regulators shut down in accordance with
Table 6, page 24) until the die temperature falls by the
thermal hysteresis amount, at which time the 5.0 V and 3.3 V
regulators will restart and the supervisor circuit will issue a full
length reset pulse. The system will then perform a normal
restart. The purpose of this circuitry is to prevent damage to
the 34921 owing to inadvertent high dissipation in the motor
drivers.
Table 6. Regulator Shutdown Schedule
Condition
XDCMA⁽²⁶⁾ XDCMB^{(26) SX}
SX 5.0 V V_CORE 3.3 V
Fault Registers
RST
0
0
OFF OFF ON
ON
ON _{Updated at falling RST}
TSD and RST
Z
Z
OFF OFF OFF ON OFF _{Updated at falling RST}
TSDCore and RST
Z
Z
OFF OFF OFF OFF OFF _{Updated at falling RST}
Notes
26. XDCMA and XDCMB: 0 means low-side ON, 1 means high-side ON, Z means both OFF.
Other Data
Registers
Default value
Default value
Default value
ANALOG ENCODER INTERFACE
Introduction
The analog encoder interface is intended to provide a
complete interface for an analog quadrature encoder, such
as an Agilent Technologies HEDS-9710/HEDS-9711 series
of analog output small optical encoder modules.
The Agilent HEDS-9710/HEDS-9711 incremental analog
quadrature encoder is a 200 lpi encoder that outputs a
quadrature analog current reflecting the position of the
encoder codewheel/codestrip within the encoder. The analog
encoder interface must provide six functions to support this
encoder: force a bias point of 1.3 V, current-to-voltage
conversion, offset current nulling, output amplitude adjust
(variable gain), channel inversion, and digital phase
generation (see Figure 12).
Note: Freescale does not assume liability, endorse, or
warrant components from external manufacturers that are
referenced in this document. While Freescale offers
component recommendations, it is the customer’s
responsibility to validate their application.
ENC_FILTA
AN2/ANALOGIN_A
A
Variable Gain
Amplifier
1.3 V
A
-1
AN3/ANALOGIN_B
Variable Gain
Amplifier
ENC_FILTB
B
B
-1
Figure 12. Analog Encoder Interface Block Diagram
A
To ADC
A
DENCA
To Serial
Interface
DENCB
B
B ^{To ADC}
34921
24
Analog Integrated Circuit Device Data
Freescale Semiconductor