OV6630 Datasheet, PDF (20/29 Pages) List of Unclassifed Manufacturers – SINGLE-CHIP CMOS CIF COLOR DIGITAL CAMERA

SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS
during read cycle, the master returns acknowledge except the read
data is the last byte. The master does not perform acknowledge if the
read data is the last byte, indicates that the slave can terminate the
read cycle. Note that the restart feature is not supported here.
Within each byte, MSB is always transferred first. Read/write control
bit is the LSB of the first byte.
Standard I²C communications require only two pins: SCL and SDA.
SDA is configured as open drain for bi-directional purpose. A HIGH
to LOW transition on the SDA while SCL is HIGH indicates a
START condition. A LOW to HIGH transition on the SDA while
SCL is HIGH indicates a STOP condition. Only a master can generate
START/STOP conditions.
Except for these two special conditions, the protocol that SDA remain
stable during the HIGH period of the clock, SCL. Each bit is allowed
to change state only when SCL is LOW (See Figure * and Figure 10
below).
The OV6630/OV6130 I²C supports multi-byte write and multi-byte
read. The master must supply the sub-address. in the write cycle, but
not in the read cycle.
SDA
SCL
DATA
STABLE
DATA CHANGE
ALLOWED
Figure 9. Bit Transfer on the I²C Bus
SDA
RW
SLAVD ID
SUB ADD
DATA
SCL
S
A
A
A
P
Figure 10. Data Transfer on the I²C Bus
Therefore, OV6630/OV6130 takes the read sub-address from the
previous write cycle. In multi-byte write or multi-byte read cycles, the
sub-address is automatically increment after the first data byte so that
continuous locations can be accessed in one bus cycle. A multi-byte
cycle overwrites its original sub-address; therefore, if a read cycle
immediately follows a multi-byte cycle, you must insert a single byte
write cycle that provides a new sub-address.
OV6630/OV6130 can be power up pin programmed to one-of-eight
slave ID addresses through function pins CS[2:0] (pins 35, 37, 34,
respectively).
Table 15. Slave ID Addresses
CS[2:0]
000
001
010
WRITE ID (hex)
C0
C4
C8
READ ID (hex)
C1
C5
C9
OV6630/OV6130 supports both single chip and multiple chip
configurations. By asserting MULT (pin 47) to high, the sensor can be
programmed for up to 8 slave ID addresses. Asserting MULT low
011
100
101
110
111
CC
D0
D4
D8
DC
CD
D1
D5
D9
DD
configures OV6630/OV6130 for single ID slave address with address
C0 for writes and address C1 for reads. MULT is internally defaulted
to a low condition.
March 4, 2000
Version 1.0
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