OV6630 Datasheet, PDF (16/29 Pages) List of Unclassifed Manufacturers – SINGLE-CHIP CMOS CIF COLOR DIGITAL CAMERA

SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS
t_SU:DAT
Data setup time
t_SU:STP
Setup time for STOP status
Digital Timing
t_PCLK
PCLK cycle time
16-bit operation
8-bit operation
t_r, t_f
PCLK rise/fall time
t_PDD
PCLK to data valid
t_PHD
PCLK to HREF delay
0.1
µs
0.6
µs
112
ns
56
15
ns
15
ns
20
10
5
ns
Table 13. Zoom Video Port AC Parameters
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
Parameter
PCLK fall time
PCLK low time
PCLK rise time
PCLK high time
PCLK period
Y/UV/HREF setup time
Y/UV/HREF hold time
VSYNC setup/hold time to HREF
Min Max
4ns
8ns
50ns
4ns
8ns
50ns
106ns
10ns
20ns
1µs
Notes:
1.
2.
3.
4.
In Interlaced Mode, there are even/odd field different (t8). When In Progressive Scan Mode, only frame timing same as Even
field(t8).
After VSYNC falling edge, OV6630 will output black reference level, the line number is T_VS, which is the line number be-
tween the 1st HREF rising edge after VSYNC falling edge and 1st valid data CHSYNC rising edge. Then valid data, then
black reference, line number is T_VE, which is the line number between last valid data CHSYNC rising edge and 1st CHSYNC
rising edge after VSYNC rising edge. The black reference output line number is dependent on vertical window setting.
When in default setting, T_VE = 14 × T_LINE, which is changed with register VS[7:0]. VS[7:0] step equal to 1 line.
When in default setting, T_VE = 4 × T_LINE for Odd Field, T_VE = 3 × T_LINE for Even Field, which is changed with register
VE[7:0]. VE[7:0] step equal to 1 line.
March 4, 2000
Version 1.0
16