OV6630 Datasheet, PDF (19/29 Pages) List of Unclassifed Manufacturers – SINGLE-CHIP CMOS CIF COLOR DIGITAL CAMERA

SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS
3 I²C Bus
Many of the functions and configuration registers in the
OV6630/OV6130 image sensors are available through the I²C
interface. The I²C port is enabled by asserting the I2CB line (pin 12)
through a 10KΩ resistor to V_DD. When the I²C capability is enabled
(I2CB = 1), the OV6630/OV6130 imager operates as a slave device
that supports up to 400 KBps serial transfer rate using a 7-bit
address/data transfer protocol.
1ST BYTE
2ND BYTE
3RD BYTE
S SLAVE ID (7BITS) RW A SUB-ADDRESS (8BITS) A
DATA (8BITS)
AP
START MSB
LSB=0
ACK
MASTER TRANSMIT, SLAVE RECEIVE (WRITE CYCLE)
1ST BYTE
2ND BYTE
ACK STOP
S SLAVE ID (7BITS) RW A SUB-ADDRESS (8BITS) A P
START ^MSB
LSB=0
ACK STOP
MASTER TRANSMIT, SLAVE RECEIVE (DUMMY WRITE CYCLE)
1ST BYTE
2ND BYTE
3RD BYTE
S SLAVE ID (7BITS) RW A
DATA (8BITS)
A
DATA (8BITS)
1P
START ^MSB
SLAVE ID - 110CCC0X
CS2 (PIN 35)
CS1 (PIN 37)
CS0 (PIN 34)
X - RW BIT, 1:READ, 0:WRITE
LSB=1
ACK
MASTER RECEIVE, SLAVE TRANSMIT (READ CYCLE)
STOP
NO ACK IN
LAST BYTE
S - START CONDITION
A - ACKNOWLEDGE BIT
P - STOP CONDITION
– SLAVE TRANSMIT
– MASTER TRANSMIT
– MASTER INITIATE
Figure 8. I²C Bus Protocol Format
3.1 I2C Bus Protocol Format
In I²C operation, the master must perform the following operations:
- Generate the start/stop condition
- Provide the serial clock on SCL
- Place the 7-bit slave address, the RW bit, and the 8-bit sub-
address on SDA
The receiver must pull down SDA during the acknowledge period.
During the write cycle, OV6630/OV6130 returns acknowledge and,
March 4, 2000
Version 1.0
19