OV6630 Datasheet, PDF (11/29 Pages) List of Unclassifed Manufacturers – SINGLE-CHIP CMOS CIF COLOR DIGITAL CAMERA

SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS
Default mode:
- 1st HREF Y channel output unstable data, UV output B₁₁ G₁₂ B₁₃ G₁₄ ···
- 2nd HREF Y channel output G₂₁ R₂₂ G₂₃ R₂₄ ···, UV output B₁₁ G₁₂ B₁₃ G₁₄ ···
- 3rd HREF Y channel output G₂₁ R₂₂ G₂₃ R₂₄ ···, UV output B₃₁ G₂₃ B₃₃ G₃₄ ···
- Every line of data is output twice.
YG mode:
- 1st HREF Y and UV output unstable data.
- 2nd HREF Y channel output G₂₁ G₁₂ G₂₃ G₁₄ ···, UV output B₁₁ R₂₂ B₁₃ R₂₄ ···
- 3rd HREF Y is G₂₁ G₃₂ G₂₃ G₃₄ ···, UV channel is B₃₁ R₂₂ B₃₃ R₂₄ ···
- Every line data output twice.
One line mode:
- 1st HREF Y channel output B₁₁ G₁₂ B₁₃ G₁₄ ···
- 2nd HREF Y channel output G₂₁ R₂₂ G₂₃ R₂₄ ···
- UV channel tri-state.
2. 8-bit Format (Total 292 HREFs)
- 1st HREF Y channel output unstable data.
- 2nd HREF Y channel output B₁₁ G₂₁ R₂₂ G₁₂ ···
- 3rd HREF Y channel output B₃₁ G₂₁ R₂₂ G₃₂ ···
- PCLK timing is doubled and PCLK rising edge latch data bus. UV channel tri-state. Every line data output twice.
3. 4-bit Nibble Mode Output Format
- Uses higher 4 bits of Y port (Y[7:4]) as output port.
- Supports YCrCb/RGB data, ITU-601/ITU-656 timing, Color/B&W.
- Output sequence: High order 4 bits followed by lower order 4 bits
Y0_H Y0_L Y1_H Y1_L ···
U0_H U0_L V0_H V0_L ···
For B/W or one-line RGB raw data, the output data clock speed is doubled. For color YUV, output clock is four times that of the 16-bit
output data. In color mode, sensor must be set to 8-bit mode, and the nibble timing, clock divided by 2.
Output sequence: U0_H U0_L Y0_H Y0_L V0_H V0_L Y1_H Y1_L ···
1.2.7 Slave Mode Operation
The OV6630/OV6130 can be programmed to operate in slave mode
(COMI[6] = 1, default is master mode). HSYNC and VSYNC output
signals are provided.
When used as a slave device, the external master must provide the
following clocks to OV6630/OV6130 imager:
1. System clock CLK to XCLK1 pin
2. Horizontal sync, HSYNC, to CHSYNC pin, positive assertion
3. Vertical frame sync, VSYNC, to VSYNC pin, positive assertion
In slave mode, the OV6630/OV6130 tri-states CHSYNC (pin 42) and
VSYNC (pin 16) output pins, and used as input pins. To synchronize
multiple devices, OV6630/OV6130 uses external system clock, CLK,
to synchronize external horizontal sync, HSYNC, which is then used
to synchronize external vertical frame sync, VSYNC. See Figure 6.
Slave Mode External Sync Timing for timing considerations.
1.2.8 Frame Exposure Mode
OV6630/OV6130 supports frame. FREX (pin 4) is asserted by an
external master device to set exposure time. The pixel array is quickly
pre-charged when FREX is set to “1”. OV6630/OV6130 captures the
image in the time period when FREX remains high. The video data
stream is delivered to output port in a line-by-line manner after FREX
switches to “0”.
It should be noted that FREX must remain high long enough to ensure
the entire image array has been pre-charged.
When data is being output from OV6630/OV6130, care must be taken
so as not to expose the image array to light. This may affect the
integrity of the image data captured. A mechanical shutter synchro-
nized with the frame exposure rate can be used to minimize this
situation. The timing of frame exposure is shown in Figure 7. Frame
Exposure Timing below.
1.2.9 Reset
OV6630/OV6130 includes a RESET pin (pin 2) that forces a
complete hardware reset when it is pulled high (VCC).
OV6630/OV6130 clears all registers and resets to their default values
when a hardware reset occurs. Reset can also be initiated through the
I²C interface.
1.2.10 Power Down Mode
Two methods are available to place OV6630/OV6130 into power-
down mode: hardware power down and I²C software power down.
To initiate hardware power down, the PWDN pin (pin 9) must be tied
to high (+3.3VDC). When this occurs, OV6630/OV6130 internal
device clock is halted and all internal counters are reset. The current
draw is less than 10µA in this standby mode.
March 4, 2000
Version 1.0
11