OV6630 Datasheet, PDF (12/29 Pages) List of Unclassifed Manufacturers – SINGLE-CHIP CMOS CIF COLOR DIGITAL CAMERA

SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS
Executing a software power down through the I²C interface suspends
internal circuit activity, but does not halt the device clock. The current
requirements drop to less than 1mA in this mode.
1.2.11 Configure OV6630/OV6130
Two methods are provided to configure OV6630/OV6130 for specific
application requirements.
At power up, OV6630/OV6130 reads the status of certain pins to
determine what, if any, power up pin programming default settings
are requested. Once the reading of the external pins status is
completed, the device configures its internal registers according to the
specified pins. Not all device functions are available for configuration
through external pins. Power up pin programming occurs in 1024
system clock cycles.
A more flexible and comprehensive method to configure
OV6630/OV6130 is to use its on-chip I²C register programming
capability. The I²C interface provides access to all of the device’s
programmable internal registers. See I2C Bus Protocol Format for
further details about using the I²C interface on the OV6630/OV6130
camera device.
CLK
HSYNC
T_CLK
T_HS
VSYNC
1 Line=472 T_CLK
1 Frame=625 x 472 T_CLK
T_VS
Notes:
T_HS > 6 T_CLK (2), T_HS < T_VS < 472 T_CLK
HSYNC period is (472 T_CLK)
VSYNC period is (625 x 472 T_CLK)
OV6630/OV6130 will be stable after 1 field (2nd VSYNC)
Figure 6. Slave Mode External Sync Timing
March 4, 2000
Version 1.0
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