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OV6630 Datasheet, PDF (13/29 Pages) List of Unclassifed Manufacturers – SINGLE-CHIP CMOS CIF COLOR DIGITAL CAMERA
SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS
FREX
TIN
TSET
HSYNC
Mechanical Shutter Off
THS
Precharge begins at the rising edge of HSYNC
ARRAY
PRECHARGE
DATA
OUTPUT
TPR
Array Exposure Period TEX
Array Precharge Period TPR
1 Frame (292 Lines) Valid Data
Invalid Data
Black Data
VSYNC
THD Head of Valid Data (8 Lines)
Next Frame
HREF
Note:
TPR=292 x 4 x TCLK. TCLK is internal pixel period. TCLK=112ns if the system clock is 17.73MHz. TCLK will
increase with the clock divider CLK[5:0].
TEX is array exposure time which is decided by external master device.
TIN is uncertain time due to the using of HSYNC rising edge to synchronize FREX. TIN < THS.
There are 8 lines data output before valid data after FREX=0. THD=4 THS. Valid data is output when
HREF=1.
TSET=TIN + TPR + TEX. TSET > TPR + TIN. The exposure time setting resolution is THS (one line) due to the
uncertainty of TIN.
Figure 7. Frame Exposure Timing
March 4, 2000
Version 1.0
13