M13S2561616A-2S Datasheet, PDF (7/49 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
IDD Specifications
Symbol
-5
IDD0
80
IDD1
110
IDD2P
4
IDD2F
30
IDD2Q
30
IDD3P
25
IDD3N
55
IDD4R
130
IDD4W
130
IDD5
140
IDD6
3
IDD7
220
Version
M13S2561616A (2S)
Operation Temperature Condition -40°C~85°C
Unit
-6
70
mA
100
mA
4
mA
30
mA
30
mA
20
mA
50
mA
120
mA
120
mA
130
mA
3
mA
210
mA
Input / Output Capacitance
Parameter
Package Symbol
Min
Max
Delta Cap
(max)
Unit
Note
Input capacitance (A0~A12, BA0~BA1, _TSOP
CKE, CS , RAS , CAS , WE )
BGA
C_IN1
2
TBD
5
TBD
pF
0.5
1,4
pF
Input capacitance (CLK, CLK )
TSOP
C_IN2
BGA
2
TBD
4
TBD
pF
0.25
1,4
pF
Data & DQS input/output capacitance
TSOP
BGA
C_OUT
1
TBD
4
TBD
pF
0.5
1,2,3,4
pF
Input capacitance (DM)
TSOP
C_IN3
BGA
1
TBD
4
TBD
pF
0.5
1,2,3,4
pF
Notes:
1. These values are guaranteed by design and are tested on a sample basis only.
2. Although DM is an input -only pin, the input capacitance of this pin must model the input capacitance of the DQ and
DQS pins. This is required to match signal propagation times of DQ, DQS, and DM in the system.
3. Unused pins are tied to ground.
4. This parameter is sampled. V_DDQ = 2.5V ± 0.2V, V_DD = 2.5V ± 0.2V. f=100MHz, T_A =25°C, V_OUT(DC) = V_DDQ/2, V_OUT
(peak to peak) = 0.2V. DM inputs are grouped with I/O pins - reflecting the fact that they are matched in loading (to
facilitate trace matching at the board level).
Elite Semiconductor Memory Technology Inc.
Publication Date : Jan. 2015
Revision : 1.0
7/49