M13S2561616A-2S Datasheet, PDF (36/49 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
Write followed by Precharge (@ BL=4)
0
1
CLK
CLK
2
3
CKE
M13S2561616A (2S)
Operation Temperature Condition -40°C~85°C
4
5
6
7
8
9
10
HIGH
CS
RAS
CAS
BA0,BA1
BAa
BAa
A10/AP
ADDR
Ca
(A0~An)
WE
DQS
tWR
DQ
DM
COMMAND
Da0 Da1 Da2 Da3
WRITE
PRE
CHARGE
: Don’t care
10122B16R.B
Elite Semiconductor Memory Technology Inc.
Publication Date : Jan. 2015
Revision : 1.0
36/49