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| M13S2561616A-2S Datasheet, PDF (34/49 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle | |||
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ESMT
Read with Auto Precharge (@ BL=8)
0
1
CLK
CLK
2
3
CKE
M13S2561616A (2S)
Operation Temperature Condition -40°C~85°C
4
5
6
7
8
9
10
HIGH
CS
RAS
CAS
BA0,BA1
BAa
A10/AP
ADDR
Ca
(A0~An)
WE
DQS(CL=2.5)
DQ(CL=2.5)
BAa
Ra
Auto precharge start
tRP
Note1
Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 Qa6 Qa7
DQS(CL=3)
DQ(CL=3)
DM
COMMAND
READ
Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 Qa6 Qa7
ACTIVE
Note: 1. The row active command of the precharge bank can be issued after tRP from this point.
The new read/write command of another activated bank can be issued from this point.
At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.
: Donât care
10122B16R.B1
Elite Semiconductor Memory Technology Inc.
Publication Date : Jan. 2015
Revision : 1.0
34/49
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