M13S2561616A-2S Datasheet, PDF (1/49 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
M13S2561616A (2S)
Operation Temperature Condition -40°C~85°C
DDR SDRAM
4M x 16 Bit x 4 Banks
Double Data Rate SDRAM
Features
z Double-data-rate architecture, two data transfers per clock cycle
z Bi-directional data strobe (DQS)
z Differential clock inputs (CLK and CLK )
z DLL aligns DQ and DQS transition with CLK transition
z Four bank operation
z CAS Latency : 2.5, 3, 4
z Burst Type : Sequential and Interleave
z Burst Length : 2, 4, 8
z All inputs except data & DM are sampled at the rising edge of the system clock (CLK)
z Data I/O transitions on both edges of data strobe (DQS)
z DQS is edge-aligned with data for READs; center-aligned with data for WRITEs
z Data mask (DM) for write masking only
z V_DD = 2.5V ± 0.2V, V_DDQ = 2.5V ± 0.2V
z 7.8us refresh interval
z Auto & Self refresh
z 2.5V I/O (SSTL_2 compatible)
Ordering Information
Product ID
Max Freq.
M13S2561616A -5TIG2S
200MHz (DDR400)
M13S2561616A -6TIG2S
166MHz (DDR333)
M13S2561616A -5BIG2S
200MHz (DDR400)
M13S2561616A -6BIG2S
166MHz (DDR333)
V_DD
2.5V
Package
Comments
66 pin TSOPII
60 Ball BGA
Pb-free
Elite Semiconductor Memory Technology Inc.
Publication Date : Jan. 2015
Revision : 1.0
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