M13S2561616A-2S Datasheet, PDF (3/49 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
PIN CONFIGURATION (TOP VIEW)
(TSOPII 66L, 400milX875mil Body, 0.65mm Pin Pitch)
M13S2561616A (2S)
Operation Temperature Condition -40°C~85°C
BALL CONFIGURATION (TOP VIEW)
(BGA60, 8mmX13mmX1.0mm Body, 0.8mm Ball Pitch)
1
2
3
A ^{VSSQ DQ15 VSS}
B ^{DQ14 VDDQ DQ13}
C DQ12 VSSQ DQ11
D DQ10 VDDQ DQ9
E DQ8 VSSQ UDQS
F VREF VSS _UDM
G
CLK CLK
H
A12 CKE
J
A11 A9
K
A8
A7
L
A6
A5
M
A4
VSS
7
8
9
VDD DQ0 VDDQ
DQ2 VSSQ DQ1
DQ4 VDDQ DQ3
DQ6 VSSQ DQ5
LDQS VDDQ DQ7
LDM VDD NC
WE CAS
RAS ^CS
BA1 BA0
A0 A10/AP
A2
A1
VDD
A3
Pin Description
Pin Name
Function
Pin Name
Function
A0~A12,
BA0, BA1
Address inputs
- Row address A0~A12
- Column address A0~A8
A10/AP: AUTO Precharge
BA0, BA1: Bank selects (4 Banks)
DM is an input mask signal for write data.
LDM, UDM LDM corresponds to the data on DQ0~DQ7;
UDM correspond to the data on DQ8~DQ15.
DQ0~DQ15 Data-in/Data-out
CLK, CLK ^{Clock input}
RAS
Row address strobe
CAS
Column address strobe
WE
Write enable
V_SS
Ground
V_DD
LDQS, UDQS
Power
Bi-directional Data Strobe.
LDQS corresponds to the data on DQ0~DQ7;
UDQS correspond to the data on DQ8~DQ15.
CKE
CS
V_DDQ
V_SSQ
V_REF
NC
Clock enable
Chip select
Supply Voltage for DQ
Ground for DQ
Reference Voltage for SSTL_2
No connection
Elite Semiconductor Memory Technology Inc.
Publication Date : Jan. 2015
Revision : 1.0
3/49