M13S128168A_1 Datasheet, PDF (7/49 Pages) Elite Semiconductor Memory Technology Inc. – 2M x 16 Bit x 4 Banks Double Data Rate SDRAM

ESMT
M13S128168A
Operation temperature condition -40°C~85°C
AC Timing Parameter & Specifications-continued
Parameter
Symbol
-5
min
Half Clock Period
DQ-DQS output hold time
Data hold skew factor
ACTIVE to PRECHARGE
command
t_HP
t_QH
t_QHS
t_RAS
t_CLmin or t_CHmin
t_HP-t_QHS
-
40
Row Cycle Time
t_RC
60
AUTO REFRESH Row Cycle
Time
t_RFC
70
ACTIVE to READ,WRITE
delay
t_RCD
15
PRECHARGE command
period
t_RP
15
ACTIVE to READ with
AUTOPRECHARGE
command
t_RAP
18
ACTIVE bank A to ACTIVE
bank B command
t_RRD
10
Write recovery time
t_WR
15
Write data in to READ
command delay
t_WTR
2
Col. Address to Col. Address
delay
t_CCD
1
Average periodic refresh
interval
t_REFI
-
Write preamble
Write postamble
DQS read preamble
DQS read postamble
Clock to DQS write preamble
setup time
t_WPRE
t_WPST
t_RPRE
t_RPST
t_WPRES
0.25
0.4
0.9
0.4
0
Load Mode Register /
Extended Mode register
t_MRD
2
cycle time
Exit self refresh to READ
command
t_XSRD
200
Exit self refresh to
non-READ command
Autoprecharge write
recovery+Precharge time
t_XSNR
t_DAL
75
(t_WR/t_CK)
+
(t_RP/t_CK)
max
-
-
0.45
70K
-
-
-
-
-
-
-
-
-
15.6
-
0.6
1.1
0.6
-
-
-
-
-6
min
t_CLmin or t_CHmin
t_HP-t_QHS
-
42
60
72
18
18
max
-
-
0.5
70K
-
-
-
-
18
-
12
-
15
-
2
-
1
-
-
15.6
0.25
-
0.4
0.6
0.9
1.1
0.4
0.6
0
-
1
-
200
-
75
-
(t_WR/t_CK)
+
(t_RP/t_CK)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t_CK
t_CK
us
t_CK
t_CK
t_CK
t_CK
ns
t_CK
t_CK
ns
t_CK
Elite Semiconductor Memory Technology Inc.
Publication Date : Mar. 2009
Revision : 1.2
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