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M13S128168A_1 Datasheet, PDF (1/49 Pages) Elite Semiconductor Memory Technology Inc. – 2M x 16 Bit x 4 Banks Double Data Rate SDRAM
ESMT
DDR SDRAM
Features
M13S128168A
Operation temperature condition -40°C~85°C
2M x 16 Bit x 4 Banks
Double Data Rate SDRAM
z JEDEC Standard
z Internal pipelined double-data-rate architecture, two data access per clock cycle
z Bi-directional data strobe (DQS)
z On-chip DLL
z Differential clock inputs (CLK and CLK )
z DLL aligns DQ and DQS transition with CLK transition
z Quad bank operation
z CAS Latency : 3
z Burst Type : Sequential and Interleave
z Burst Length : 2, 4, 8
z All inputs except data & DM are sampled at the rising edge of the system clock(CLK)
z Data I/O transitions on both edges of data strobe (DQS)
z DQS is edge-aligned with data for reads; center-aligned with data for WRITE
z Data mask (DM) for write masking only
z VDD = 2.375V ~ 2.75V, VDDQ = 2.375V ~ 2.75V
z Auto & Self refresh
z 15.6us refresh interval (64ms refresh period, 4K cycle)
z SSTL-2 I/O interface
z 66pin TSOPII and 60 Ball BGA package
Ordering information :
PRODUCT NO.
M13S128168A -5TIG
M13S128168A -6TIG
M13S128168A -5BIG
M13S128168A -6BIG
MAX FREQ
200MHz
166MHz
200MHz
166MHz
VDD
2.5V
2.5V
PACKAGE
TSOPII
BGA
COMMENTS
Pb-free
Pb-free
Pb-free
Pb-free
Elite Semiconductor Memory Technology Inc.
Publication Date : Mar. 2009
Revision : 1.2
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