M13S128168A_1 Datasheet, PDF (32/49 Pages) Elite Semiconductor Memory Technology Inc. – 2M x 16 Bit x 4 Banks Double Data Rate SDRAM

ESMT
M13S128168A
Operation temperature condition -40°C~85°C
Basic Timing (Setup, Hold and Access Time @ BL=4, CL=3)
CLK
CLK
CKE
CS
RAS
CAS
BA0,BA1
A10/AP
ADDR
(A0~An)
WE
DQS
DQ
DM
COMMAND
0
1
BAa
BAa
READ
tCL
tCK
2
3
4
5
6
7
8
9
10
HIGH
tHP
Note1
tIS
tIH
BAb
Cb
tDQSCK
tRPRE
tLZ
tDQSCK
tRPST
Hi-Z
tDQSQ
Da0 Da1
Da2
tAC
Da3
tHZ
Hi-Z
tQH
tDQSS
tWPRE
tDQSL
t
W
P
R
E
t
S
D
Q
S
H
tDS tDH tDS tDH
Db0 Db1 Db2
tWPST
Db3
Hi-Z
Hi-Z
WRITE
Note 1. tHP is lesser of tCL or tCH clock transition collectively when a bank is active.
Elite Semiconductor Memory Technology Inc.
Publication Date : Mar. 2009
Revision : 1.2
32/49