M13S128168A_1 Datasheet, PDF (21/49 Pages) Elite Semiconductor Memory Technology Inc. – 2M x 16 Bit x 4 Banks Double Data Rate SDRAM

ESMT
M13S128168A
Operation temperature condition -40°C~85°C
Write Interrupted by a Precharge & DM
A burst write operation can be interrupted before completion of the burst by a precharge of the same bank. Random column
access is allowed. A write recovery time (t_WR) is required from the last data to precharge command. When precharge command is
asserted, any residual data from the burst write cycle must be masked by DM.
<Burst Length = 8>
0
1
CLK
CLK
2
3
4
5
6
7
8
COMMAND
NOP
DQS
DQ's
DQS
WRITE A
NOP
tDQSSmax
NOP
NOP
NOP
Precharge WRITE B
NOP
tDQSSmin
tWR
Dina0 Dina1 Dina2 Dina3 Dina4 Dina5 Dina6 Dina7
tWR
Dinb0
DQ's
Dina0 Dina1 Dina2 Dina3 Dina4 Dina5 Dina6 Dina7
Dinb0 Dinb1
DM
Precharge timing for Write operations in DRAMs requires enough time to allow “Write recovery” which is the time required by a
DRAM core to properly store a full “0” or “1” level before a Precharge operation. For DDR SDRAM, a timing parameter, t_WR, is used
to indicate the required of time between the last valid write operation and a Precharge command to the same bank.
The precharge timing for writes is a complex definition since the write data is sampled by the data strobe and the address is
sampled by the input clock. Inside the SDRAM, the data path is eventually synchronizes with the address path by switching clock
domains from the data strobe clock domain to the input clock domain.
This makes the definition of when a precharge operation can be initiated after a write very complex since the write recovery
parameter must reference only the clock domain that is used to time the internal write operation i.e., the input clock domain.
t_WR starts on the rising clock edge after the last possible DQS edge that strobed in the last valid and ends on the rising clock
edge that strobes in the precharge command.
Elite Semiconductor Memory Technology Inc.
Publication Date : Mar. 2009
Revision : 1.2
21/49