M13S128168A_1 Datasheet, PDF (23/49 Pages) Elite Semiconductor Memory Technology Inc. – 2M x 16 Bit x 4 Banks Double Data Rate SDRAM

ESMT
M13S128168A
Operation temperature condition -40°C~85°C
The Burst Stop command is a mandatory feature for DDR SDRAMs. The following functionality is required.
1. The BST command may only be issued on the rising edge of the input clock, CLK.
2. BST is only a valid command during Read burst.
3. BST during a Write burst is undefined and shall not be used.
4. BST applies to all burst lengths.
5. BST is an undefined command during Read with autoprecharge and shall not be used.
6. When terminating a burst Read command, the BST command must be issued L_BST ( “BST Latency”) clock cycles before the
clock edge at which the output buffers are tristated, where L_BST equals the CAS latency for read operations.
7. When the burst terminates, the DQ and DQS pins are tristated.
The BST command is not byte controllable and applies to all bits in the DQ data word and the (all) DQS pin(s).
DM masking
The DDR SDRAM has a data mask function that can be used in conjunction with data write cycle. Not read cycle. When the
data mask is activated (DM high) during write operation, DDR SDRAM does not accept the corresponding data. (DM to data-mask
latency is zero) DM must be issued at the rising or falling edge of data strobe.
<Burst Length = 8>
0
1
CLK
CLK
COMMAND ^WRITE
NOP
DQS
tDQSS
2
3
NOP
NOP
4
NOP
5
6
NOP
NOP
7
NOP
8
NOP
DQ's
Din 0 Din 1 Din 2 Din 3 Din 4 Din 5 Din 6 Din 7
DM
masked by DM = H
Elite Semiconductor Memory Technology Inc.
Publication Date : Mar. 2009
Revision : 1.2
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