M11L416256SA Datasheet, PDF (5/16 Pages) Elite Semiconductor Memory Technology Inc. – 256 K x 16 DRAM EDO PAGE MODE

EliteMT
(Continued)
PARAMETER
SYMBOL
Read Command Hold Time Reference to CAS
Read Command Hold Time Reference to RAS
CAS to Output in Low-Z
Output Buffer Turn-off Delay From CAS or
RAS
Output Buffer Turn-off to OE
Write Command Setup Time
Write Command Hold Time
Write Command Hold Time(Reference to RAS )
Write Command Pulse Width
Write Command to RAS Lead Time
Write Command to CAS Lead Time
Data-in Setup Time
Data-in Hold Time
Data-in Hold Time (Reference to RAS )
RAS to WE Delay Time
Column Address to WE Delay Time
CAS to WE Delay Time
Transition Time (rise or fall)
Refresh Period (512 cycles)
RAS to CAS Precharge Time
CAS Setup Time(CBR REFRESH)
CAS Hold Time(CBR REFRESH)
OE Hold Time From WE During
Read-Mode-Write Cycle
OE Low to CAS High Setup Time
OE High Hold Time From CAS High
OE Precharge Time
OE Setup Prior to RAS During Hidden
Refresh Cycle
Last CAS Going Low to First CAS
Returning High
Data Output Hold After CAS Returning Low
Output Disable Delay From WE
Self Refresh RAS Low Pulse width
Self Refresh RAS High Precharge Time
Self Refresh CAS Hold Time
tRCH
tRRH
tCLZ
tOFF1
tOFF2
tWCS
tWCH
tWCR
tWP
tRWL
tCWL
tDS
tDH
tDHR
tRWD
tAWD
tCWD
tT
tREF
tRPC
tCSR
tCHR
tOEH
tOES
tOEHC
tOEP
tORD
tCLCH
tCOH
tWHZ
tRASS
tRPS
tCHS
-35
MIN
MAX
0
0
3
3
15
8
0
5
30
5
9
7
0
5
30
51
34
26
2.5
50
8
10
10
10
4
4
2
2
0
5
3
3
7
100
65
-50
M11L416256SA
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
ns
ns
NOTES
9,15,19
9
20
10,17,20
17,26
11,15,18
15,25
15
15
15
15,19
12,20
12,20
11
11
11,18
2,3
1,18
1,19
16
21
27,28
27,28
27,28
Elite Memory Technology Inc
Publication Date: Aug. 2005
Revision : 1.4
5/16