M11L416256SA Datasheet, PDF (4/16 Pages) Elite Semiconductor Memory Technology Inc. – 256 K x 16 DRAM EDO PAGE MODE

EliteMT
M11L416256SA
CAPACITANCE (Ta = 25 °C , VCC = 3.3V ± 10%)
PARAMETER
SYMBOL
TYP
Input Capacitance (address)
CI1
-
Input Capacitance ( RAS , CASH , CASL , WE , OE )
CI2
-
Output capacitance (I/O0~I/O15)
CI / O
-
MAX
5
7
10
UNIT
pF
pF
pF
AC ELECTRICAL CHARACTERISTICS (Ta = 0 to 70 °C , VCC =3.3V ± 10%, VSS = 0V) (note 14)
Test Conditions
Input timing reference levels : 0.8V, 2.0V
Output reference level : VOL= 0.8V, VOH=2.0V
Output Load : 2TTL gate + CL (50pF)
Assumed tT = 2ns
PARAMETER
SYMBOL
-35
MIN
MAX
UNIT
NOTES
Read or Write Cycle Time
tRC
65
ns
Read Write Cycle Time
tRWC
95
ns
EDO-Page-Mode Read or Write Cycle
Time
tPC
14
ns
22
EDO-Page-Mode Read-Write Cycle
Time
tPCM
42
ns
22
Access Time From RAS
tRAC
35
ns
4
Access Time From CAS
tCAC
10
ns
5,20
Access Time From OE
tOAC
Access Time From Column Address
tAA
Access Time From CAS Precharge
tACP
10
ns
13,20
18
ns
20
ns
20
RAS Pulse Width
tRAS
35
10K
ns
RAS Pulse Width (EDO Page Mode)
tRASC
35
100K
ns
RAS Hold Time
RAS Precharge Time
tRSH
10
tRP
25
ns
25
ns
CAS Pulse Width
CAS Hold Time
CAS Precharge Time
RAS to CAS Delay Time
tCAS
5
tCSH
30
tCP
5
tRCD
10
10K
ns
24
ns
19
ns
6,23
25
ns
7,18
CAS to RAS Precharge Time
tCRP
5
Row Address Setup Time
tASR
0
Row Address Hold Time
tRAH
5
RAS to Column Address Delay Time
tRAD
8
Column Address Setup Time
tASC
0
Column Address Hold Time
tCAH
5
Column Address Hold Time (Reference
to RAS )
tAR
30
ns
19
ns
ns
17
ns
8
ns
18
ns
18
ns
Column Address to RAS Lead Time
tRAL
18
Read Command Setup Time
tRCS
0
ns
15,18
Elite Memory Technology Inc
Publication Date: Aug. 2005
Revision : 1.4
4/16