SED1565 Datasheet, PDF (79/87 Pages) Epson Company – Direct display of RAM data through the display data RAM

Item
Serial Clock Period
SCL “H” pulse width
SCL “L” pulse width
Address setup time
Address hold time
Data setup time
Data hold time
CS-SCL time
SED1565 Series
Signal
SCL
A0
SI
CS
Table 33
(VDD = 2.7 V to 4.5 V, Ta = –40 to 85°C )
Symbol
Condition
Rating
Min
Max
Units
tSCYC
tSHW
tSLW
250
—
ns
100
—
ns
100
—
ns
tSAS
tSAH
150
—
ns
150
—
ns
tSDS
tSDH
100
—
ns
100
—
ns
tCSS
tCSH
150
—
ns
150
—
ns
Item
Serial Clock Period
SCL “H” pulse width
SCL “L” pulse width
Address setup time
Address hold time
Data setup time
Data hold time
CS-SCL time
Signal
SCL
A0
SI
CS
Table 34
(VDD = 1.8 V to 2.7 V, Ta = –40 to 85°C )
Symbol
Condition
Rating
Min
Max
Units
tSCYC
tSHW
tSLW
400
—
ns
150
—
ns
150
—
ns
tSAS
tSAH
250
—
ns
250
—
ns
tSDS
tSDH
150
—
ns
150
—
ns
tCSS
tCSH
250
—
ns
250
—
ns
*1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less.
*2 All timing is specified using 20% and 80% of VDD as the standard.
EPSON
8–77