SED1565 Datasheet, PDF (77/87 Pages) Epson Company – Direct display of RAM data through the display data RAM

SED1565 Series
Item
Address hold time
Address setup time
System cycle time
Data setup time
Data hold time
Access time
Output disable time
Enable H pulse
time
Read
Write
Enable L pulse
time
Read
Write
Signal
A0
A0
D0 to D7
E
E
Table 30
(VDD = 2.7 V to 4.5 V, Ta = –40 to 85°C )
Symbol
Condition
Rating
Min
Max
Units
tAH6
tAW6
0
—
ns
0
—
ns
tCYC6
300
—
ns
tDS6
40
—
ns
tDH6
15
—
ns
tACC6
tOH6
CL = 100 pF
—
140
ns
10
100
ns
tEWHR
tEWHW
120
—
ns
60
—
ns
tEWLR
tEWLW
60
—
ns
60
—
ns
Table 31
(VDD = 1.8 V to 2.7 V, Ta = –40 to 85°C )
Item
Address hold time
Address setup time
System cycle time
Data setup time
Data hold time
Access time
Output disable time
Enable H pulse
time
Read
Write
Enable L pulse
time
Read
Write
Signal
A0
A0
D0 to D7
E
E
Symbol
tAH6
tAW6
tCYC6
tDS6
tDH6
tACC6
tOH6
tEWHR
tEWHW
tEWLR
tEWLW
Condition
CL = 100 pF
Rating
Min
Max
0
—
0
—
1000
—
80
—
30
—
—
280
10
200
240
—
120
—
120
—
120
—
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is
extremely fast, (tr + tf) ≤ (tCYC6 – tEWLW – tEWHW) for (tr + tf) ≤ (tCYC6 – tEWLR – tEWHR) are specified.
*2 All timing is specified using 20% and 80% of VDD as the reference.
*3 tEWLW and tEWLR are specified as the overlap between CS1 being “L” (CS2 = “H”) and E.
EPSON
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