SED1565 Datasheet, PDF (75/87 Pages) Epson Company – Direct display of RAM data through the display data RAM

SED1565 Series
Item
Signal
Address hold time
Address setup time
System cycle time
Control L pulse width (WR)
Control L pulse width (RD)
Control H pulse width (WR)
Control H pulse width (RD)
Data setup time
Address hold time
RD access time
Output disable time
A0
A0
WR
RD
WR
RD
D0 to D7
Table 27
(VDD = 2.7 V to 4.5 V, Ta = –40 to 85°C )
Symbol
Condition
Rating
Min
Max
Units
tAH8
tAW8
0
—
ns
0
—
ns
tCYC8
300
—
ns
tCCLW
tCCLR
tCCHW
tCCHR
60
—
ns
120
—
ns
60
—
ns
60
—
ns
tDS8
40
—
ns
tDH8
15
—
ns
tACC8
tOH8
CL = 100 pF
—
140
ns
10
100
ns
Item
Signal
Address hold time
Address setup time
System cycle time
Control L pulse width (WR)
Control L pulse width (RD)
Control H pulse width (WR)
Control H pulse width (RD)
Data setup time
Address hold time
RD access time
Output disable time
A0
A0
WR
RD
WR
RD
D0 to D7
Table 28
(VDD = 1.8 V to 2.7 V, Ta = –40 to 85°C )
Symbol
Condition
Rating
Min
Max
Units
tAH8
tAW8
0
—
ns
0
—
ns
tCYC8
1000
—
ns
tCCLW
tCCLR
tCCHW
tCCHR
120
—
ns
240
—
ns
120
—
ns
120
—
ns
tDS8
tDH8
80
—
ns
30
—
ns
tACC8
tOH8
CL = 100 pF
—
280
ns
10
200
ns
*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is
extremely fast, (tr + tf) ≤ (tCYC8 – tCCLW – tCCHW) for (tr + tf) ≤ (tCYC8 – tCCLR – tCCHR) are specified.
*2 All timing is specified using 20% and 80% of VDD as the reference.
*3 tCCLW and tCCLR are specified as the overlap between CS1 being “L” (CS2 = “H”) and WR and RD being
at the “L” level.
EPSON
8–73